The mlx5 datapath does not implement any endianness conversions
for the metadata being sent and received to provide the better
performance (because these conversions would be performed for
each packet). These metadata are also involved into flow processing
(there might be some flows matching on metadata patterns or setting
the new metadata values) inside the NIC. It order to configure
hardware in correct way all necessary endianness conversions are
done by rte_flow handling code (only once on flow creation). This
patch fixes one of these conversions for the little-endian hosts
in case if META/MARK items are less than 32 bits.
Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: sta...@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viachesl...@mellanox.com>
Acked-by: Matan Azrad <ma...@mellanox.com>
---
v1: - http://patchwork.dpdk.org/patch/64125/
v2: - commit message is rewritten
drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index dd21bc6..e8a764c 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5909,8 +5909,12 @@ struct field_modify_info modify_tcp[] = {
struct mlx5_priv *priv = dev->data->dev_private;
uint32_t msk_c0 = priv->sh->dv_regc0_mask;
uint32_t shl_c0 = rte_bsf32(msk_c0);
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+ uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
- msk_c0 = rte_cpu_to_be_32(msk_c0);
+ value >>= shr_c0;
+ mask >>= shr_c0;
+#endif
value <<= shl_c0;
mask <<= shl_c0;
assert(msk_c0);
--
1.8.3.1
