26/12/2019 02:46, Wu, Jingjing:
> From: Li, Xiaoyun <xiaoyun...@intel.com>
> > All buffers and ring info should be written before tail register update.
> > This patch relocates the write memory barrier before updating tail register
> > to avoid potential issues.
> >
> > Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions")
> > Cc: sta...@dpdk.org
> >
> > Signed-off-by: Xiaoyun Li <xiaoyun...@intel.com>
> Acked-by: Jingjing Wu <jingjing...@intel.com>v1 applied, thanks
