If core 0 is not included in coremask in event mode then
ipsec-secgw seg faults. This fix uses first core from
coremask in rx queue configuration instead of core 0
which was always previously used.
Signed-off-by: Lukasz Bartosik <lbarto...@marvell.com>
---
examples/ipsec-secgw/ipsec-secgw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/ipsec-secgw/ipsec-secgw.c
b/examples/ipsec-secgw/ipsec-secgw.c
index ce36e6d..5fde4f7 100644
--- a/examples/ipsec-secgw/ipsec-secgw.c
+++ b/examples/ipsec-secgw/ipsec-secgw.c
@@ -2643,7 +2643,7 @@ check_event_mode_params(struct eh_conf *eh_conf)
params = &lcore_params[nb_lcore_params++];
params->port_id = portid;
params->queue_id = 0;
- params->lcore_id = 0;
+ params->lcore_id = rte_get_next_lcore(0, 0, 1);
}
return 0;
--
2.7.4
