From: Nithin Dabilpuram <ndabilpu...@marvell.com>
Disable CQ_DISABLED error interrupt in NIX_LF_ERR_INT
to fix spurious interrupts in event dev mode. Also skip
configuring RSS when RQ count is '0' because
RSS table initialization is done incorrectly due to
divide-by-zero error and it is leading to RQ_OOR error
in NIX_LF_ERR_INT.
Fixes: 83ce2880e22e ("net/octeontx2: support RSS")
Cc: vattun...@marvell.com
Cc: sta...@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
---
drivers/net/octeontx2/otx2_ethdev_irq.c | 7 +++++--
drivers/net/octeontx2/otx2_rss.c | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c
b/drivers/net/octeontx2/otx2_ethdev_irq.c
index 96b848a..b121488 100644
--- a/drivers/net/octeontx2/otx2_ethdev_irq.c
+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c
@@ -472,9 +472,12 @@ otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev,
bool enb)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
- /* Enable all nix lf error interrupts except for RQ_DISABLED */
+ /* Enable all nix lf error interrupts except
+ * RQ_DISABLED and CQ_DISABLED.
+ */
if (enb)
- otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+ otx2_write64(~(BIT_ULL(11) | BIT_ULL(24)),
+ dev->base + NIX_LF_ERR_INT_ENA_W1S);
else
otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
}
diff --git a/drivers/net/octeontx2/otx2_rss.c b/drivers/net/octeontx2/otx2_rss.c
index a29441e..5e3f866 100644
--- a/drivers/net/octeontx2/otx2_rss.c
+++ b/drivers/net/octeontx2/otx2_rss.c
@@ -358,7 +358,7 @@ otx2_nix_rss_config(struct rte_eth_dev *eth_dev)
int rc;
/* Skip further configuration if selected mode is not RSS */
- if (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS)
+ if (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS || !qcnt)
return 0;
/* Update default RSS key and cfg */
--
2.8.4
