Hello, On Tue, Jan 27, 2015 at 5:49 AM, ??? <wuyd at outlook.com> wrote:
> 65 bytes frame may degrade performace a lot.Thats related to DMA and cache. > When NIC dma packets to memory, NIC has to do read modify write if DMA > size is partial cache line.So for 65 bytes, the first 64 bytes are ok. The > next 1 byte NIC has to read the whole cache line, change one byte and > update the cache line. > So in DPDK, CRC is not stripped and ethernet header aligned to cache line > which causes ip header not aligned on 4 bytes. > > Extra cache line update indeed makes sense because performance is halved with extra byte. It is a little bit confusing, but the issue is not with switching from 64 bytes frames to 65 bytes frames, but with switching from 80 bytes frame to 81 bytes frame. Note that the issue disappears at 96 bytes frame size. Alexander
