On Fri, Aug 21, 2020 at 12:29 PM <kirankum...@marvell.com> wrote:
>
> From: Kiran Kumar K <kirankum...@marvell.com>
>
> When TX side VTAG insertion is enabled, As we are not setting the max
> vtag insertion size an interrupt has been received. This patch will fix
> the issue by configuring the max vtag insertion size to 8B.
>
> Signed-off-by: Kiran Kumar K <kirankum...@marvell.com>
Updated git comment to provide more detail while applying:
``
net/octeontx2: set max vtag insertion size
When TX side VTAG insertion is enabled, SMQ should be configured with
the maximum VTAG insertion size to avoid generating NIX_SQINT_SEND_ERR
interrupt. Since the default value is zero, This patch configures the
VTAG insertion size to the max supported value.
Signed-off-by: Kiran Kumar K <kirankum...@marvell.com>
Acked-by: Jerin Jacob <jer...@marvell.com>
``
Applied to dpdk-next-net-mrvl/main. Thanks
> ---
> drivers/net/octeontx2/otx2_tm.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c
> index 8ed059549..b76242a60 100644
> --- a/drivers/net/octeontx2/otx2_tm.c
> +++ b/drivers/net/octeontx2/otx2_tm.c
> @@ -560,8 +560,9 @@ populate_tm_reg(struct otx2_eth_dev *dev,
> * smaller
> */
> reg[k] = NIX_AF_SMQX_CFG(schq);
> - regval[k] = BIT_ULL(50) | NIX_MIN_HW_FRS;
> - regval_mask[k] = ~(BIT_ULL(50) | 0x7f);
> + regval[k] = BIT_ULL(50) | ((uint64_t)NIX_MAX_VTAG_INS << 36) |
> + NIX_MIN_HW_FRS;
> + regval_mask[k] = ~(BIT_ULL(50) | (0x7ULL << 36) | 0x7f);
> k++;
>
> /* Parent and schedule conf */
> --
> 2.25.1
>
