All bits in FDIRTCPM and FDIRUDPM are set to 1 when
ixgbe_fdir_set_input_mask_82599 is called. Not settings these bits will cause
TCP and UDP packets to be filtered out when NVGRE or VXLAN mode is enabled.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu at intel.com>
---
drivers/net/ixgbe/base/ixgbe_82599.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c
b/drivers/net/ixgbe/base/ixgbe_82599.c
index d3d8c6f..90de625 100644
--- a/drivers/net/ixgbe/base/ixgbe_82599.c
+++ b/drivers/net/ixgbe/base/ixgbe_82599.c
@@ -1915,7 +1915,12 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
}
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
- /* Set all bits in FDIRSIP4M and FDIRDIP4M cloud mode */
+ /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
+ * FDIRDIP4M in cloud mode to allow L3/L3 packets to
+ * tunnel.
+ */
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
}
--
1.9.3
