From: Chengwen Feng <fengcheng...@huawei.com>
The TM QCN error event should report by RAS other than MSIX.
Also this patch adds fifo int enable configuration before the TM QCN
error event is enabled.
Fixes: f53a793bb7c2 ("net/hns3: add more hardware error types")
Fixes: 3903c05382c5 ("net/hns3: remove read when enabling TM QCN error event")
Cc: sta...@dpdk.org
Signed-off-by: Chengwen Feng <fengcheng...@huawei.com>
Signed-off-by: Min Hu (Connor) <humi...@huawei.com>
---
drivers/net/hns3/hns3_intr.c | 5 ++++-
drivers/net/hns3/hns3_intr.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c
index 905c6d9..6bdb17f 100644
--- a/drivers/net/hns3/hns3_intr.c
+++ b/drivers/net/hns3/hns3_intr.c
@@ -1783,8 +1783,11 @@ enable_tm_err_intr(struct hns3_adapter *hns, bool en)
/* configure TM QCN hw errors */
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, false);
- if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_TM_QCN_ERR_INT_TYPE);
+ if (en) {
+ desc.data[0] |= rte_cpu_to_le_32(HNS3_TM_QCN_FIFO_INT_EN);
desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
+ }
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
diff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h
index 8bee8d7..1a0f196 100644
--- a/drivers/net/hns3/hns3_intr.h
+++ b/drivers/net/hns3/hns3_intr.h
@@ -77,6 +77,8 @@
#define HNS3_NCSI_ERR_INT_EN 0x3
#define HNS3_TM_SCH_ECC_ERR_INT_EN 0x3
+#define HNS3_TM_QCN_ERR_INT_TYPE 0x29
+#define HNS3_TM_QCN_FIFO_INT_EN 0xFFFF00
#define HNS3_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
#define HNS3_RESET_PROCESS_MS 200
--
2.7.4
