Add support for packet type lookup on Rx to translate HW
specific types to RTE_PTYPE_* defines
Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
---
doc/guides/nics/cnxk.rst | 1 +
doc/guides/nics/features/cnxk.ini | 1 +
doc/guides/nics/features/cnxk_vec.ini | 1 +
doc/guides/nics/features/cnxk_vf.ini | 1 +
drivers/net/cnxk/cn10k_ethdev.c | 21 +++
drivers/net/cnxk/cn10k_rx.h | 11 ++
drivers/net/cnxk/cn9k_ethdev.c | 21 +++
drivers/net/cnxk/cn9k_rx.h | 12 ++
drivers/net/cnxk/cnxk_ethdev.c | 2 +
drivers/net/cnxk/cnxk_ethdev.h | 14 ++
drivers/net/cnxk/cnxk_lookup.c | 326 ++++++++++++++++++++++++++++++++++
drivers/net/cnxk/meson.build | 3 +-
12 files changed, 413 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/cnxk/cn10k_rx.h
create mode 100644 drivers/net/cnxk/cn9k_rx.h
create mode 100644 drivers/net/cnxk/cnxk_lookup.c
diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index 7bf6cf5..8bc85c0 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -16,6 +16,7 @@ Features
Features of the CNXK Ethdev PMD are:
+- Packet type information
- SR-IOV VF
- Lock-free Tx queue
- Multiple queues for TX and RX
diff --git a/doc/guides/nics/features/cnxk.ini
b/doc/guides/nics/features/cnxk.ini
index 462d7c4..503582c 100644
--- a/doc/guides/nics/features/cnxk.ini
+++ b/doc/guides/nics/features/cnxk.ini
@@ -14,6 +14,7 @@ Runtime Rx queue setup = Y
Runtime Tx queue setup = Y
RSS hash = Y
Inner RSS = Y
+Packet type parsing = Y
Linux = Y
ARMv8 = Y
Usage doc = Y
diff --git a/doc/guides/nics/features/cnxk_vec.ini
b/doc/guides/nics/features/cnxk_vec.ini
index 09e0d3a..9ad225a 100644
--- a/doc/guides/nics/features/cnxk_vec.ini
+++ b/doc/guides/nics/features/cnxk_vec.ini
@@ -14,6 +14,7 @@ Runtime Rx queue setup = Y
Runtime Tx queue setup = Y
RSS hash = Y
Inner RSS = Y
+Packet type parsing = Y
Linux = Y
ARMv8 = Y
Usage doc = Y
diff --git a/doc/guides/nics/features/cnxk_vf.ini
b/doc/guides/nics/features/cnxk_vf.ini
index 4a93a35..8c93ba7 100644
--- a/doc/guides/nics/features/cnxk_vf.ini
+++ b/doc/guides/nics/features/cnxk_vf.ini
@@ -13,6 +13,7 @@ Runtime Rx queue setup = Y
Runtime Tx queue setup = Y
RSS hash = Y
Inner RSS = Y
+Packet type parsing = Y
Linux = Y
ARMv8 = Y
Usage doc = Y
diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 454c8ca..f79d03c 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -2,8 +2,25 @@
* Copyright(C) 2021 Marvell.
*/
#include "cn10k_ethdev.h"
+#include "cn10k_rx.h"
#include "cn10k_tx.h"
+static int
+cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+ if (ptype_mask) {
+ dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
+ dev->ptype_disable = 0;
+ } else {
+ dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
+ dev->ptype_disable = 1;
+ }
+
+ return 0;
+}
+
static void
nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,
uint16_t qid)
@@ -114,6 +131,9 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev,
uint16_t qid,
/* Data offset from data to start of mbuf is first_skip */
rxq->data_off = rq->first_skip;
rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
+
+ /* Lookup mem */
+ rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
return 0;
}
@@ -149,6 +169,7 @@ nix_eth_dev_ops_override(void)
cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;
cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup;
cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;
+ cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
}
static int
diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
new file mode 100644
index 0000000..d3d1661
--- /dev/null
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#ifndef __CN10K_RX_H__
+#define __CN10K_RX_H__
+
+#include <rte_ether.h>
+
+#define NIX_RX_OFFLOAD_PTYPE_F BIT(1)
+
+#endif /* __CN10K_RX_H__ */
diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
index a8ac2c5..b5a4bd7 100644
--- a/drivers/net/cnxk/cn9k_ethdev.c
+++ b/drivers/net/cnxk/cn9k_ethdev.c
@@ -2,8 +2,25 @@
* Copyright(C) 2021 Marvell.
*/
#include "cn9k_ethdev.h"
+#include "cn9k_rx.h"
#include "cn9k_tx.h"
+static int
+cn9k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+ if (ptype_mask) {
+ dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
+ dev->ptype_disable = 0;
+ } else {
+ dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
+ dev->ptype_disable = 1;
+ }
+
+ return 0;
+}
+
static void
nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,
uint16_t qid)
@@ -112,6 +129,9 @@ cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev,
uint16_t qid,
/* Data offset from data to start of mbuf is first_skip */
rxq->data_off = rq->first_skip;
rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
+
+ /* Lookup mem */
+ rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get();
return 0;
}
@@ -158,6 +178,7 @@ nix_eth_dev_ops_override(void)
cnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;
cnxk_eth_dev_ops.tx_queue_setup = cn9k_nix_tx_queue_setup;
cnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;
+ cnxk_eth_dev_ops.dev_ptypes_set = cn9k_nix_ptypes_set;
}
static int
diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h
new file mode 100644
index 0000000..95a1e69
--- /dev/null
+++ b/drivers/net/cnxk/cn9k_rx.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __CN9K_RX_H__
+#define __CN9K_RX_H__
+
+#include <rte_ether.h>
+
+#define NIX_RX_OFFLOAD_PTYPE_F BIT(1)
+
+#endif /* __CN9K_RX_H__ */
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 0a11081..6a0bd50 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -860,6 +860,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = {
.link_update = cnxk_nix_link_update,
.tx_queue_release = cnxk_nix_tx_queue_release,
.rx_queue_release = cnxk_nix_rx_queue_release,
+ .dev_supported_ptypes_get = cnxk_nix_supported_ptypes_get,
};
static int
@@ -899,6 +900,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
dev->eth_dev = eth_dev;
dev->configured = 0;
+ dev->ptype_disable = 0;
/* For vfs, returned max_entries will be 0. but to keep default mac
* address, one entry must be allocated. so setting up to 1.
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index ef8e408..b23df4a 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -91,6 +91,15 @@
#define RSS_SCTP_INDEX 4
#define RSS_DMAC_INDEX 5
+#define PTYPE_NON_TUNNEL_WIDTH 16
+#define PTYPE_TUNNEL_WIDTH 12
+#define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
+#define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
+#define PTYPE_ARRAY_SZ
\
+ ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
+/* Fastpath lookup */
+#define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
+
struct cnxk_eth_qconf {
union {
struct rte_eth_txconf tx;
@@ -119,6 +128,7 @@ struct cnxk_eth_dev {
uint8_t max_mac_entries;
uint16_t flags;
+ uint8_t ptype_disable;
bool scalar_ena;
/* Pointer back to rte */
@@ -216,6 +226,10 @@ void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
struct roc_nix_link_info *link);
int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
+/* Lookup configuration */
+const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
+void *cnxk_nix_fastpath_lookup_mem_get(void);
+
/* Devargs */
int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
struct cnxk_eth_dev *dev);
diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c
new file mode 100644
index 0000000..0152ad9
--- /dev/null
+++ b/drivers/net/cnxk/cnxk_lookup.c
@@ -0,0 +1,326 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include <rte_common.h>
+#include <rte_memzone.h>
+
+#include "cnxk_ethdev.h"
+
+/* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
+#define ERRCODE_ERRLEN_WIDTH 12
+#define ERR_ARRAY_SZ ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
+
+#define SA_TBL_SZ (RTE_MAX_ETHPORTS * sizeof(uint64_t))
+#define LOOKUP_ARRAY_SZ (PTYPE_ARRAY_SZ + ERR_ARRAY_SZ + SA_TBL_SZ)
+const uint32_t *
+cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev)
+{
+ RTE_SET_USED(eth_dev);
+
+ static const uint32_t ptypes[] = {
+ RTE_PTYPE_L2_ETHER_QINQ, /* LB */
+ RTE_PTYPE_L2_ETHER_VLAN, /* LB */
+ RTE_PTYPE_L2_ETHER_TIMESYNC, /* LB */
+ RTE_PTYPE_L2_ETHER_ARP, /* LC */
+ RTE_PTYPE_L2_ETHER_NSH, /* LC */
+ RTE_PTYPE_L2_ETHER_FCOE, /* LC */
+ RTE_PTYPE_L2_ETHER_MPLS, /* LC */
+ RTE_PTYPE_L3_IPV4, /* LC */
+ RTE_PTYPE_L3_IPV4_EXT, /* LC */
+ RTE_PTYPE_L3_IPV6, /* LC */
+ RTE_PTYPE_L3_IPV6_EXT, /* LC */
+ RTE_PTYPE_L4_TCP, /* LD */
+ RTE_PTYPE_L4_UDP, /* LD */
+ RTE_PTYPE_L4_SCTP, /* LD */
+ RTE_PTYPE_L4_ICMP, /* LD */
+ RTE_PTYPE_L4_IGMP, /* LD */
+ RTE_PTYPE_TUNNEL_GRE, /* LD */
+ RTE_PTYPE_TUNNEL_ESP, /* LD */
+ RTE_PTYPE_TUNNEL_NVGRE, /* LD */
+ RTE_PTYPE_TUNNEL_VXLAN, /* LE */
+ RTE_PTYPE_TUNNEL_GENEVE, /* LE */
+ RTE_PTYPE_TUNNEL_GTPC, /* LE */
+ RTE_PTYPE_TUNNEL_GTPU, /* LE */
+ RTE_PTYPE_TUNNEL_VXLAN_GPE, /* LE */
+ RTE_PTYPE_TUNNEL_MPLS_IN_GRE, /* LE */
+ RTE_PTYPE_TUNNEL_MPLS_IN_UDP, /* LE */
+ RTE_PTYPE_INNER_L2_ETHER, /* LF */
+ RTE_PTYPE_INNER_L3_IPV4, /* LG */
+ RTE_PTYPE_INNER_L3_IPV6, /* LG */
+ RTE_PTYPE_INNER_L4_TCP, /* LH */
+ RTE_PTYPE_INNER_L4_UDP, /* LH */
+ RTE_PTYPE_INNER_L4_SCTP, /* LH */
+ RTE_PTYPE_INNER_L4_ICMP, /* LH */
+ RTE_PTYPE_UNKNOWN,
+ };
+
+ return ptypes;
+}
+
+/*
+ * +------------------ +------------------ +
+ * | | IL4 | IL3| IL2 | TU | L4 | L3 | L2 |
+ * +-------------------+-------------------+
+ *
+ * +-------------------+------------------ +
+ * | | LH | LG | LF | LE | LD | LC | LB |
+ * +-------------------+-------------------+
+ *
+ * ptype [LE - LD - LC - LB] = TU - L4 - L3 - T2
+ * ptype_tunnel[LH - LG - LF] = IL4 - IL3 - IL2 - TU
+ *
+ */
+static void
+nix_create_non_tunnel_ptype_array(uint16_t *ptype)
+{
+ uint8_t lb, lc, ld, le;
+ uint16_t val;
+ uint32_t idx;
+
+ for (idx = 0; idx < PTYPE_NON_TUNNEL_ARRAY_SZ; idx++) {
+ lb = idx & 0xF;
+ lc = (idx & 0xF0) >> 4;
+ ld = (idx & 0xF00) >> 8;
+ le = (idx & 0xF000) >> 12;
+ val = RTE_PTYPE_UNKNOWN;
+
+ switch (lb) {
+ case NPC_LT_LB_STAG_QINQ:
+ val |= RTE_PTYPE_L2_ETHER_QINQ;
+ break;
+ case NPC_LT_LB_CTAG:
+ val |= RTE_PTYPE_L2_ETHER_VLAN;
+ break;
+ }
+
+ switch (lc) {
+ case NPC_LT_LC_ARP:
+ val |= RTE_PTYPE_L2_ETHER_ARP;
+ break;
+ case NPC_LT_LC_NSH:
+ val |= RTE_PTYPE_L2_ETHER_NSH;
+ break;
+ case NPC_LT_LC_FCOE:
+ val |= RTE_PTYPE_L2_ETHER_FCOE;
+ break;
+ case NPC_LT_LC_MPLS:
+ val |= RTE_PTYPE_L2_ETHER_MPLS;
+ break;
+ case NPC_LT_LC_IP:
+ val |= RTE_PTYPE_L3_IPV4;
+ break;
+ case NPC_LT_LC_IP_OPT:
+ val |= RTE_PTYPE_L3_IPV4_EXT;
+ break;
+ case NPC_LT_LC_IP6:
+ val |= RTE_PTYPE_L3_IPV6;
+ break;
+ case NPC_LT_LC_IP6_EXT:
+ val |= RTE_PTYPE_L3_IPV6_EXT;
+ break;
+ case NPC_LT_LC_PTP:
+ val |= RTE_PTYPE_L2_ETHER_TIMESYNC;
+ break;
+ }
+
+ switch (ld) {
+ case NPC_LT_LD_TCP:
+ val |= RTE_PTYPE_L4_TCP;
+ break;
+ case NPC_LT_LD_UDP:
+ val |= RTE_PTYPE_L4_UDP;
+ break;
+ case NPC_LT_LD_SCTP:
+ val |= RTE_PTYPE_L4_SCTP;
+ break;
+ case NPC_LT_LD_ICMP:
+ case NPC_LT_LD_ICMP6:
+ val |= RTE_PTYPE_L4_ICMP;
+ break;
+ case NPC_LT_LD_IGMP:
+ val |= RTE_PTYPE_L4_IGMP;
+ break;
+ case NPC_LT_LD_GRE:
+ val |= RTE_PTYPE_TUNNEL_GRE;
+ break;
+ case NPC_LT_LD_NVGRE:
+ val |= RTE_PTYPE_TUNNEL_NVGRE;
+ break;
+ }
+
+ switch (le) {
+ case NPC_LT_LE_VXLAN:
+ val |= RTE_PTYPE_TUNNEL_VXLAN;
+ break;
+ case NPC_LT_LE_ESP:
+ val |= RTE_PTYPE_TUNNEL_ESP;
+ break;
+ case NPC_LT_LE_VXLANGPE:
+ val |= RTE_PTYPE_TUNNEL_VXLAN_GPE;
+ break;
+ case NPC_LT_LE_GENEVE:
+ val |= RTE_PTYPE_TUNNEL_GENEVE;
+ break;
+ case NPC_LT_LE_GTPC:
+ val |= RTE_PTYPE_TUNNEL_GTPC;
+ break;
+ case NPC_LT_LE_GTPU:
+ val |= RTE_PTYPE_TUNNEL_GTPU;
+ break;
+ case NPC_LT_LE_TU_MPLS_IN_GRE:
+ val |= RTE_PTYPE_TUNNEL_MPLS_IN_GRE;
+ break;
+ case NPC_LT_LE_TU_MPLS_IN_UDP:
+ val |= RTE_PTYPE_TUNNEL_MPLS_IN_UDP;
+ break;
+ }
+ ptype[idx] = val;
+ }
+}
+
+#define TU_SHIFT(x) ((x) >> PTYPE_NON_TUNNEL_WIDTH)
+static void
+nix_create_tunnel_ptype_array(uint16_t *ptype)
+{
+ uint8_t lf, lg, lh;
+ uint16_t val;
+ uint32_t idx;
+
+ /* Skip non tunnel ptype array memory */
+ ptype = ptype + PTYPE_NON_TUNNEL_ARRAY_SZ;
+
+ for (idx = 0; idx < PTYPE_TUNNEL_ARRAY_SZ; idx++) {
+ lf = idx & 0xF;
+ lg = (idx & 0xF0) >> 4;
+ lh = (idx & 0xF00) >> 8;
+ val = RTE_PTYPE_UNKNOWN;
+
+ switch (lf) {
+ case NPC_LT_LF_TU_ETHER:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L2_ETHER);
+ break;
+ }
+ switch (lg) {
+ case NPC_LT_LG_TU_IP:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV4);
+ break;
+ case NPC_LT_LG_TU_IP6:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV6);
+ break;
+ }
+ switch (lh) {
+ case NPC_LT_LH_TU_TCP:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L4_TCP);
+ break;
+ case NPC_LT_LH_TU_UDP:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L4_UDP);
+ break;
+ case NPC_LT_LH_TU_SCTP:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L4_SCTP);
+ break;
+ case NPC_LT_LH_TU_ICMP:
+ case NPC_LT_LH_TU_ICMP6:
+ val |= TU_SHIFT(RTE_PTYPE_INNER_L4_ICMP);
+ break;
+ }
+
+ ptype[idx] = val;
+ }
+}
+
+static void
+nix_create_rx_ol_flags_array(void *mem)
+{
+ uint16_t idx, errcode, errlev;
+ uint32_t val, *ol_flags;
+
+ /* Skip ptype array memory */
+ ol_flags = (uint32_t *)((uint8_t *)mem + PTYPE_ARRAY_SZ);
+
+ for (idx = 0; idx < BIT(ERRCODE_ERRLEN_WIDTH); idx++) {
+ errlev = idx & 0xf;
+ errcode = (idx & 0xff0) >> 4;
+
+ val = PKT_RX_IP_CKSUM_UNKNOWN;
+ val |= PKT_RX_L4_CKSUM_UNKNOWN;
+ val |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
+
+ switch (errlev) {
+ case NPC_ERRLEV_RE:
+ /* Mark all errors as BAD checksum errors
+ * including Outer L2 length mismatch error
+ */
+ if (errcode) {
+ val |= PKT_RX_IP_CKSUM_BAD;
+ val |= PKT_RX_L4_CKSUM_BAD;
+ } else {
+ val |= PKT_RX_IP_CKSUM_GOOD;
+ val |= PKT_RX_L4_CKSUM_GOOD;
+ }
+ break;
+ case NPC_ERRLEV_LC:
+ if (errcode == NPC_EC_OIP4_CSUM ||
+ errcode == NPC_EC_IP_FRAG_OFFSET_1) {
+ val |= PKT_RX_IP_CKSUM_BAD;
+ val |= PKT_RX_OUTER_IP_CKSUM_BAD;
+ } else {
+ val |= PKT_RX_IP_CKSUM_GOOD;
+ }
+ break;
+ case NPC_ERRLEV_LG:
+ if (errcode == NPC_EC_IIP4_CSUM)
+ val |= PKT_RX_IP_CKSUM_BAD;
+ else
+ val |= PKT_RX_IP_CKSUM_GOOD;
+ break;
+ case NPC_ERRLEV_NIX:
+ if (errcode == NIX_RX_PERRCODE_OL4_CHK ||
+ errcode == NIX_RX_PERRCODE_OL4_LEN ||
+ errcode == NIX_RX_PERRCODE_OL4_PORT) {
+ val |= PKT_RX_IP_CKSUM_GOOD;
+ val |= PKT_RX_L4_CKSUM_BAD;
+ val |= PKT_RX_OUTER_L4_CKSUM_BAD;
+ } else if (errcode == NIX_RX_PERRCODE_IL4_CHK ||
+ errcode == NIX_RX_PERRCODE_IL4_LEN ||
+ errcode == NIX_RX_PERRCODE_IL4_PORT) {
+ val |= PKT_RX_IP_CKSUM_GOOD;
+ val |= PKT_RX_L4_CKSUM_BAD;
+ } else if (errcode == NIX_RX_PERRCODE_IL3_LEN ||
+ errcode == NIX_RX_PERRCODE_OL3_LEN) {
+ val |= PKT_RX_IP_CKSUM_BAD;
+ } else {
+ val |= PKT_RX_IP_CKSUM_GOOD;
+ val |= PKT_RX_L4_CKSUM_GOOD;
+ }
+ break;
+ }
+ ol_flags[idx] = val;
+ }
+}
+
+void *
+cnxk_nix_fastpath_lookup_mem_get(void)
+{
+ const char name[] = CNXK_NIX_FASTPATH_LOOKUP_MEM;
+ const struct rte_memzone *mz;
+ void *mem;
+
+ mz = rte_memzone_lookup(name);
+ if (mz != NULL)
+ return mz->addr;
+
+ /* Request for the first time */
+ mz = rte_memzone_reserve_aligned(name, LOOKUP_ARRAY_SZ, SOCKET_ID_ANY,
+ 0, ROC_ALIGN);
+ if (mz != NULL) {
+ mem = mz->addr;
+ /* Form the ptype array lookup memory */
+ nix_create_non_tunnel_ptype_array(mem);
+ nix_create_tunnel_ptype_array(mem);
+ /* Form the rx ol_flags based on errcode */
+ nix_create_rx_ol_flags_array(mem);
+ return mem;
+ }
+ return NULL;
+}
diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build
index 1ac3d08..5bc0bb5 100644
--- a/drivers/net/cnxk/meson.build
+++ b/drivers/net/cnxk/meson.build
@@ -11,7 +11,8 @@ endif
sources = files('cnxk_ethdev.c',
'cnxk_ethdev_ops.c',
'cnxk_ethdev_devargs.c',
- 'cnxk_link.c')
+ 'cnxk_link.c',
+ 'cnxk_lookup.c')
# CN9K
sources += files('cn9k_ethdev.c')
--
2.8.4
