>-----Original Message----- >From: David Marchand <david.march...@redhat.com> >Sent: Tuesday, July 20, 2021 4:33 PM >To: Pavan Nikhilesh Bhagavatula <pbhagavat...@marvell.com> >Cc: Jerin Jacob Kollanukkaran <jer...@marvell.com>; Shijith Thotton ><sthot...@marvell.com>; dev <dev@dpdk.org> >Subject: [EXT] Re: [dpdk-dev] [PATCH v9 2/7] event/cnxk: add Rx >adapter fastpath ops > >External Email > >---------------------------------------------------------------------- >On Wed, Jul 14, 2021 at 11:02 AM <pbhagavat...@marvell.com> wrote: >> >> From: Pavan Nikhilesh <pbhagavat...@marvell.com> >> >> Add support for event eth Rx adapter fastpath operations. >> >> Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com> > >This patch triggers a build issue for arm64 cross compiling on my >system with a 8.3 toolchain from Linaro. >I ended up upgrading my toolchain (which solved the issue), but some >users might hit this, so posting for info:
This is a known compiler bug https://bugs.dpdk.org/show_bug.cgi?id=697 > > >[2813/2834] Compiling C object >drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c. >o >FAILED: >drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c. >o >aarch64-linux-gnu-gcc -Idrivers/libtmp_rte_event_cnxk.a.p -Idrivers >-I../../dpdk/drivers -Idrivers/event/cnxk >-I../../dpdk/drivers/event/cnxk -Ilib/eventdev >-I../../dpdk/lib/eventdev -I. -I../../dpdk -Iconfig >-I../../dpdk/config -Ilib/eal/include -I../../dpdk/lib/eal/include >-Ilib/eal/linux/include -I../../dpdk/lib/eal/linux/include >-Ilib/eal/arm/include -I../../dpdk/lib/eal/arm/include >-Ilib/eal/common -I../../dpdk/lib/eal/common -Ilib/eal >-I../../dpdk/lib/eal -Ilib/kvargs -I../../dpdk/lib/kvargs >-Ilib/metrics -I../../dpdk/lib/metrics -Ilib/telemetry >-I../../dpdk/lib/telemetry -Ilib/ring -I../../dpdk/lib/ring >-Ilib/ethdev -I../../dpdk/lib/ethdev -Ilib/net -I../../dpdk/lib/net >-Ilib/mbuf -I../../dpdk/lib/mbuf -Ilib/mempool >-I../../dpdk/lib/mempool -Ilib/meter -I../../dpdk/lib/meter -Ilib/hash >-I../../dpdk/lib/hash -Ilib/rcu -I../../dpdk/lib/rcu -Ilib/timer >-I../../dpdk/lib/timer -Ilib/cryptodev -I../../dpdk/lib/cryptodev >-Idrivers/bus/pci -I../../dpdk/drivers/bus/pci >-I../../dpdk/drivers/bus/pci/linux -Ilib/pci -I../../dpdk/lib/pci >-Idrivers/common/cnxk -I../../dpdk/drivers/common/cnxk -Ilib/security >-I../../dpdk/lib/security -Idrivers/net/cnxk >-I../../dpdk/drivers/net/cnxk -Idrivers/bus/vdev >-I../../dpdk/drivers/bus/vdev -Idrivers/mempool/cnxk >-I../../dpdk/drivers/mempool/cnxk -fdiagnostics-color=always -pipe >-D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O2 -g -include >rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat >-Wformat-nonliteral -Wformat-security -Wmissing-declarations >-Wmissing-prototypes -Wnested-externs -Wold-style-definition >-Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef >-Wwrite-strings -Wno-packed-not-aligned >-Wno-missing-field-initializers -D_GNU_SOURCE -fPIC -march=armv8- >a+crc >-DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API -Wno-format- >truncation >-flax-vector-conversions -Wno-strict-aliasing >-DRTE_LOG_DEFAULT_LOGTYPE=pmd.event.cnxk -MD -MQ >drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c. >o -MF >drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c. >o.d -o >drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c. >o -c >../../dpdk/drivers/event/cnxk/cn10k_worker_deq.c >{standard input}: Assembler messages: >{standard input}:1392: Error: reg pair must start from even reg at >operand 1 -- `caspl x23,x24,x23,x24,[x2]' >{standard input}:10473: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:15726: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:19146: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x4]' >{standard input}:28825: Error: reg pair must start from even reg at >operand 1 -- `caspl x7,x8,x7,x8,[x3]' >{standard input}:30845: Error: reg pair must start from even reg at >operand 1 -- `caspl x27,x28,x27,x28,[x2]' >{standard input}:34301: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x3]' >{standard input}:40152: Error: reg pair must start from even reg at >operand 1 -- `caspl x7,x8,x7,x8,[x2]' >{standard input}:44998: Error: reg pair must start from even reg at >operand 1 -- `caspl x7,x8,x7,x8,[x2]' >{standard input}:52457: Error: reg pair must start from even reg at >operand 1 -- `caspl x27,x28,x27,x28,[x2]' >{standard input}:58407: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:62121: Error: reg pair must start from even reg at >operand 1 -- `caspl x7,x8,x7,x8,[x4]' >{standard input}:64121: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:67572: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x4]' >{standard input}:69764: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:88814: Error: reg pair must start from even reg at >operand 1 -- `caspl x27,x28,x27,x28,[x2]' >{standard input}:92747: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x4]' >{standard input}:95490: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:99628: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x2]' >{standard input}:102765: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:115148: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x4]' >{standard input}:122005: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x4]' >{standard input}:140039: Error: reg pair must start from even reg at >operand 1 -- `caspl x21,x22,x21,x22,[x2]' >{standard input}:147676: Error: reg pair must start from even reg at >operand 1 -- `caspl x21,x22,x21,x22,[x2]' >{standard input}:154953: Error: reg pair must start from even reg at >operand 1 -- `caspl x21,x22,x21,x22,[x2]' >{standard input}:159334: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x2]' >{standard input}:162769: Error: reg pair must start from even reg at >operand 1 -- `caspl x17,x18,x17,x18,[x2]' >{standard input}:167453: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x2]' >{standard input}:171071: Error: reg pair must start from even reg at >operand 1 -- `caspl x17,x18,x17,x18,[x2]' >{standard input}:179105: Error: reg pair must start from even reg at >operand 1 -- `caspl x23,x24,x23,x24,[x2]' >{standard input}:186966: Error: reg pair must start from even reg at >operand 1 -- `caspl x23,x24,x23,x24,[x2]' >{standard input}:191653: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x3]' >{standard input}:195360: Error: reg pair must start from even reg at >operand 1 -- `caspl x15,x16,x15,x16,[x3]' >{standard input}:204312: Error: reg pair must start from even reg at >operand 1 -- `caspl x15,x16,x15,x16,[x3]' >{standard input}:209537: Error: reg pair must start from even reg at >operand 1 -- `caspl x5,x6,x5,x6,[x2]' >{standard input}:222601: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:228793: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:234946: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:240956: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:258235: Error: reg pair must start from even reg at >operand 1 -- `caspl x5,x6,x5,x6,[x2]' >{standard input}:264084: Error: reg pair must start from even reg at >operand 1 -- `caspl x5,x6,x5,x6,[x2]' >{standard input}:270355: Error: reg pair must start from even reg at >operand 1 -- `caspl x7,x8,x7,x8,[x3]' >{standard input}:272988: Error: reg pair must start from even reg at >operand 1 -- `caspl x21,x22,x21,x22,[x2]' >{standard input}:277045: Error: reg pair must start from even reg at >operand 1 -- `caspl x7,x8,x7,x8,[x3]' >{standard input}:279878: Error: reg pair must start from even reg at >operand 1 -- `caspl x21,x22,x21,x22,[x2]' >{standard input}:297340: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x3]' >{standard input}:304594: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x3]' >{standard input}:315184: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:322794: Error: reg pair must start from even reg at >operand 1 -- `caspl x19,x20,x19,x20,[x2]' >{standard input}:327357: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x2]' >{standard input}:335754: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x2]' >{standard input}:361049: Error: reg pair must start from even reg at >operand 1 -- `caspl x9,x10,x9,x10,[x3]' >{standard input}:364869: Error: reg pair must start from even reg at >operand 1 -- `caspl x15,x16,x15,x16,[x2]' >{standard input}:370062: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x3]' >{standard input}:374066: Error: reg pair must start from even reg at >operand 1 -- `caspl x15,x16,x15,x16,[x2]' >{standard input}:382804: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:391016: Error: reg pair must start from even reg at >operand 1 -- `caspl x3,x4,x3,x4,[x2]' >{standard input}:441361: Error: reg pair must start from even reg at >operand 1 -- `caspl x11,x12,x11,x12,[x3]' > > >-- >David Marchand
