On Thu, Sep 02, 2021 at 06:35:07PM +0530, Jerin Jacob wrote: > On Thu, Sep 2, 2021 at 5:13 PM Bruce Richardson > <bruce.richard...@intel.com> wrote: > > > > On Thu, Sep 02, 2021 at 04:24:18PM +0530, Jerin Jacob wrote: > > > > > > I think 25us will not be enough, e.s.p If is PCI-Dev to PCI-Dev kind > > > of test cases. > > > Since it is the functional test case, I think, we can keep it a very > > > higher range to > > > support all cases. Maybe 50ms is a good target. > > > > > > > Sure, no problem to push it up. If it turns out that all upstreamed drivers > > implement the "idle" function we can remove the fallback option completely, > > but I'll keep it for now and push timeout up. Do you really think it needs > > to be in the (tens of )millisecond range? Even for tests going across PCI > > would most transactions not complete in the microsecond range, e.g. 100 > > usec? > > Based on busload and size of buffers the completion time can vary. I > think, 1 ms could be > good trade-off. Also, In the future some HW needs beyond that then we > can increase.
Ok, thanks.
