On Thu, 20 Jan 2022 22:32:46 -0500
Wei Huang <wei.hu...@intel.com> wrote:
> @@ -497,7 +497,7 @@ static int set_surprise_link_check_aer(
> int gsd_enable, ret;
> #define MS 1000
>
> - while (1) {
> + while (rte_atomic32_read(&ifpga_monitor_start)) {
Better, but rte_atomic is deprecated in favor of using __atomic builtin
instead. This is because there are more options possible with
__atomic_load_n than rte_atomic32_read. rte_atomic32_read has to assume
worst case memory ordering, and your example relaxed memory ordering is
what you need.
