30/05/2022 11:37, Raja Zidane: > TIMER_MILLISECOND is defined as the number of cpu cycles per millisecond, > current definition is correct for cores with frequency of 2GHZ, for cores > with different frequency, it caused different periods between refresh, > (i.e. the definition is about 14ms on ARM cores). > > Use dpdk API to get CPU frequency, to define TIMER_MILLISECOND. > > Fixes: af75078fece3 ("first public release") > Cc: sta...@dpdk.org > > Signed-off-by: Raja Zidane <rzid...@nvidia.com> > Acked-by: Matan Azrad <ma...@nvidia.com> > --- > --- a/examples/link_status_interrupt/main.c > +++ b/examples/link_status_interrupt/main.c > /* A tsc-based timer responsible for triggering statistics printout */ > -#define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */ > +#define TIMER_MILLISECOND (rte_get_tsc_hz() / 1000)
It is preferred to use rte_get_timer_hz(). > #define MAX_TIMER_PERIOD 86400 /* 1 day max */ > -static int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default > period is 10 seconds */ > +#define DEFAULT_TIMER_PERIOD 10UL /* default period is 10 seconds */ > +static int64_t timer_period; [...] > + timer_period = DEFAULT_TIMER_PERIOD; After a quick look, it seems we are missing the operation * TIMER_MILLISECOND * 1000 Isn't it?