On Mon, Mar 13, 2023 at 11:10 PM Srikanth Yalavarthi <syalavar...@marvell.com> wrote: > > Add ML to the list of platform hardware accelerator blocks. > > Signed-off-by: Srikanth Yalavarthi <syalavar...@marvell.com> > --- > doc/guides/platform/cnxk.rst | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst > index aadd60b5d4..1956cc31d8 100644 > --- a/doc/guides/platform/cnxk.rst > +++ b/doc/guides/platform/cnxk.rst > @@ -76,6 +76,8 @@ DPDK subsystem. > +---+-----+--------------------------------------------------------------+ > | 12| GPIO| rte_rawdev | > +---+-----+--------------------------------------------------------------+ > + | 12| ML | rte_mldev | > + +---+-----+--------------------------------------------------------------
# It should be 13 instead of 12. # Also, please add fixes: tags and change subject accordingly With above changes: Acked-by: Jerin Jacob <jer...@marvell.com> + > > PF0 is called the administrative / admin function (AF) and has exclusive > privileges to provision RVU functional block's LFs to each of the PF/VF. > @@ -165,6 +167,9 @@ This section lists dataplane H/W block(s) available in > cnxk SoC. > #. **Regex Device Driver** > See :doc:`../regexdevs/cn9k` for REE Regex device driver information. > > +#. **ML Device Driver** > + See :doc:`../mldevs/cnxk` for Machine Learning device driver information. > + > Procedure to Setup Platform > --------------------------- > > -- > 2.17.1 >
