Most modern processor now supports numa partitioning using
sub NUMA CPU-IO & Last Level Cache within the same socket.
As per the discussion in mailing list, suggesting the make
use of hw-loc for such scenarios.
Signed-off-by: Vipin Varghese <vipin.vargh...@amd.com>
---
---
usertools/cpu_layout.py | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/usertools/cpu_layout.py b/usertools/cpu_layout.py
index 891b9238fa..48c1f06d95 100755
--- a/usertools/cpu_layout.py
+++ b/usertools/cpu_layout.py
@@ -29,6 +29,16 @@
core_map[key] = []
core_map[key].append(cpu)
+
+print("")
+print(format("=" * (55 + len(base_path))))
+print(" for more porcessors, which support sub Socket Numa & L3 Numa
clustering, please use")
+print(format("=" * (55 + len(base_path))))
+print(" - lstopo-no-graphics --no-io -.ascii (CPU Mapping)")
+print(" - lstopo-no-graphics -.ascii --whole-io --no-caches (IO device
Mapping)")
+print(format("=" * (55 + len(base_path))))
+print("")
+
print(format("=" * (47 + len(base_path))))
print("Core and Socket Information (as reported by '{}')".format(base_path))
print("{}\n".format("=" * (47 + len(base_path))))
--
2.34.1
