On Wed, Nov 22, 2023 at 5:17 PM Bruce Richardson
<bruce.richard...@intel.com> wrote:
>
> On Wed, Nov 22, 2023 at 05:02:56PM +0100, David Marchand wrote:
> > On Tue, Nov 21, 2023 at 5:49 PM <christian.ehrha...@canonical.com> wrote:
> > >
> > > From: Christian Ehrhardt <christian.ehrha...@canonical.com>
> > >
> > > If building riscv natively with -Dplatform=generic config/meson.build
> > > will select cpu_instruction_set=riscv.
> > >
> > > That was fine because config/riscv/meson.build did override it to valid
> > > values later, but since b7676fcccab4 ("config: verify machine arch
> > > flag") it will break the build as it tries to test -march=riscv which
> > > is not a value value.
> > >
> > > The generic setting used in most cases is rv64gc, set this here
> > > as well.
> > >
> > > Fixes: b7676fcccab4 ("config: verify machine arch flag")
> > > Fixes: f22e705ebf12 ("eal/riscv: support RISC-V architecture")
> > >
> > > Signed-off-by: Christian Ehrhardt <christian.ehrha...@canonical.com>
> > > ---
> > > config/meson.build | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/config/meson.build b/config/meson.build
> > > index d732154731..a9ccd56deb 100644
> > > --- a/config/meson.build
> > > +++ b/config/meson.build
> > > @@ -152,7 +152,7 @@ if cpu_instruction_set == 'generic'
> > > elif host_machine.cpu_family().startswith('ppc')
> > > cpu_instruction_set = 'power8'
> > > elif host_machine.cpu_family().startswith('riscv')
> > > - cpu_instruction_set = 'riscv'
> > > + cpu_instruction_set = 'rv64gc'
> >
> > Copying more people.
> >
> > This fix is probably the best, so close to the release.
> >
>
> Agreed
I took this patch as is, for now.
>
> >
> > However, I think a more complete fix would be to set this here to generic.
> > And do the march validation in config/riscv/meson.build in a similar
> > fashion to ARM.
> >
> > Or maybe the validation added in b7676fcccab4 ("config: verify machine
> > arch flag") should be moved after subdir(arch_subdir).
> > Bruce, opinion?
> >
>
> Probably the first of these two is best, to do the march validation in the
> riscv-specific file. However, I've no strong opinions either way.
Stanislaw, could you look at doing some enhancement on this topic?
And, in any case, what we lack is a CI for RISC V.
--
David Marchand
