On Sun, 5 May 2024 22:42:57 +0300
Abdullah Ömer Yamaç <aomerya...@gmail.com> wrote:
> > Also, this looks wrong. The initialized arrays looked better before.
> >
> >
> > -static const char *tuntap_types[ETH_TUNTAP_TYPE_MAX] = {
> > - "UNKNOWN", "TUN", "TAP"
> > -};
> > +static const char *tuntap_types[ETH_TUNTAP_TYPE_MAX] = {"UNKNOWN", "TUN",
> > "TAP"};
> >
> > -static const char *valid_arguments[] = {
> > - ETH_TAP_IFACE_ARG,
> > - ETH_TAP_REMOTE_ARG,
> > - ETH_TAP_MAC_ARG,
> > - ETH_TAP_PERSIST_ARG,
> > - NULL
> > -};
> > +static const char *valid_arguments[] = {ETH_TAP_IFACE_ARG,
> > ETH_TAP_REMOTE_ARG, ETH_TAP_MAC_ARG,
> > + ETH_TAP_PERSIST_ARG, NULL};
> >
>
> I am confused about these variables. tuntap_types list values in a single
> line, but valid_arguments' values are listed separately.
> So, it is getting more complex to handle both of them. What should we do,
> do you have any idea?
Ignore the initialized lists for now. It should be possible to have it generate
something
like
static const char *tuntap_types[ETH_TUNTAP_TYPE_MAX] = {
"UNKNOWN", "TUN", "TAP"
};
With the following changes result looks better. You got the format wrong for
the ForEach list.
diff --git a/.clang-format b/.clang-format
index 16164ef1de..d16185c049 100644
--- a/.clang-format
+++ b/.clang-format
@@ -1,12 +1,20 @@
---
BasedOnStyle: LLVM
+AttributeMacros:
+ - __rte_aligned
+ - __rte_packed
+ - __rte_may_alias
+ - __rte_deprecated
+ - __rte_weak
+ - __rte_unused
+ - __rte_restrict
+
# Place opening and closing parentheses on the same line for control statements
BreakBeforeBraces: Custom
BraceWrapping:
- AfterFunction: false
+ AfterFunction: true
AfterControlStatement: false
- AfterEnum: false
# Set maximum line length to 100 characters
ColumnLimit: 100
@@ -41,98 +49,117 @@ AlwaysBreakAfterReturnType: TopLevelDefinitions
# Always break before multiline string literals
AlignEscapedNewlines: Left
-# Foreach macros
-ForEachMacros: [
- "CIRBUF_FOREACH",
- "DLB2_LIST_FOR_EACH",
- "DLB2_LIST_FOR_EACH_SAFE",
- "ECORE_LIST_FOR_EACH_ENTRY",
- "ECORE_LIST_FOR_EACH_ENTRY_SAFE",
- "FOR_EACH",
- "FOR_EACH_BUCKET",
- "FOR_EACH_CNIC_QUEUE",
- "FOR_EACH_COS_IN_TX_QUEUE",
- "FOR_EACH_ETH_QUEUE",
- "FOR_EACH_MEMBER",
- "FOR_EACH_NONDEFAULT_ETH_QUEUE",
- "FOR_EACH_NONDEFAULT_QUEUE",
- "FOR_EACH_PORT",
- "FOR_EACH_PORT_IF",
- "FOR_EACH_QUEUE",
- "FOR_EACH_SUITE_TESTCASE",
- "FOR_EACH_SUITE_TESTSUITE",
- "FOREACH_ABS_FUNC_IN_PORT",
- "FOREACH_DEVICE_ON_AUXILIARY_BUS",
- "FOREACH_DEVICE_ON_CDXBUS",
- "FOREACH_DEVICE_ON_PCIBUS",
- "FOREACH_DEVICE_ON_PLATFORM_BUS",
- "FOREACH_DEVICE_ON_UACCEBUS",
- "FOREACH_DEVICE_ON_VMBUS",
- "FOREACH_DRIVER_ON_AUXILIARY_BUS",
- "FOREACH_DRIVER_ON_CDXBUS",
- "FOREACH_DRIVER_ON_PCIBUS",
- "FOREACH_DRIVER_ON_PLATFORM_BUS",
- "FOREACH_DRIVER_ON_UACCEBUS",
- "FOREACH_DRIVER_ON_VMBUS",
- "FOREACH_SUBDEV",
- "FOREACH_SUBDEV_STATE",
- "HLIST_FOR_EACH_ENTRY",
- "ILIST_FOREACH",
- "LIST_FOR_EACH_ENTRY",
- "LIST_FOR_EACH_ENTRY_SAFE",
- "LIST_FOREACH",
- "LIST_FOREACH_FROM",
- "LIST_FOREACH_FROM_SAFE",
- "LIST_FOREACH_SAFE",
- "ML_AVG_FOREACH_QP",
- "ML_AVG_FOREACH_QP_MVTVM",
- "ML_AVG_RESET_FOREACH_QP",
- "ML_MAX_FOREACH_QP",
- "ML_MAX_FOREACH_QP_MVTVM",
- "ML_MAX_RESET_FOREACH_QP",
- "ML_MIN_FOREACH_QP",
- "ML_MIN_FOREACH_QP_MVTVM",
- "ML_MIN_RESET_FOREACH_QP",
- "MLX5_ETH_FOREACH_DEV",
- "MLX5_IPOOL_FOREACH",
- "MLX5_L3T_FOREACH",
- "OSAL_LIST_FOR_EACH_ENTRY",
- "OSAL_LIST_FOR_EACH_ENTRY_SAFE",
- "PLT_TAILQ_FOREACH_SAFE",
- "RTE_BBDEV_FOREACH",
- "RTE_DEV_FOREACH",
- "RTE_DMA_FOREACH_DEV",
- "RTE_EAL_DEVARGS_FOREACH",
- "RTE_ETH_FOREACH_DEV",
- "RTE_ETH_FOREACH_DEV_OF",
- "RTE_ETH_FOREACH_DEV_OWNED_BY",
- "RTE_ETH_FOREACH_DEV_SIBLING",
- "RTE_ETH_FOREACH_MATCHING_DEV",
- "RTE_ETH_FOREACH_VALID_DEV",
- "RTE_GPU_FOREACH",
- "RTE_GPU_FOREACH_CHILD",
- "RTE_GPU_FOREACH_PARENT",
- "RTE_LCORE_FOREACH",
- "RTE_LCORE_FOREACH_WORKER",
- "RTE_TAILQ_FOREACH",
- "RTE_TAILQ_FOREACH_SAFE",
- "SILIST_FOREACH",
- "SLIST_FOREACH",
- "SLIST_FOREACH_FROM",
- "SLIST_FOREACH_FROM_SAFE",
- "SLIST_FOREACH_PREVPTR",
- "SLIST_FOREACH_SAFE",
- "STAILQ_FOREACH",
- "STAILQ_FOREACH_FROM",
- "STAILQ_FOREACH_FROM_SAFE",
- "STAILQ_FOREACH_SAFE",
- "TAILQ_FOREACH",
- "TAILQ_FOREACH_ENTRY",
- "TAILQ_FOREACH_ENTRY_SAFE",
- "TAILQ_FOREACH_FROM",
- "TAILQ_FOREACH_FROM_SAFE",
- "TAILQ_FOREACH_REVERSE",
- "TAILQ_FOREACH_REVERSE_FROM",
- "TAILQ_FOREACH_REVERSE_FROM_SAFE",
- "TAILQ_FOREACH_REVERSE_SAFE",
- "TAILQ_FOREACH_SAFE", ]
+ForEachMacros:
+ - CIRBUF_FOREACH
+ - DLB2_LIST_FOR_EACH
+ - DLB2_LIST_FOR_EACH_SAFE
+ - ECORE_LIST_FOR_EACH_ENTRY
+ - ECORE_LIST_FOR_EACH_ENTRY_SAFE
+ - FOREACH_ABS_FUNC_IN_PORT
+ - FOREACH_DEVICE_ON_AUXILIARY_BUS
+ - FOREACH_DEVICE_ON_CDXBUS
+ - FOREACH_DEVICE_ON_PCIBUS
+ - FOREACH_DEVICE_ON_PLATFORM_BUS
+ - FOREACH_DEVICE_ON_UACCEBUS
+ - FOREACH_DEVICE_ON_VMBUS
+ - FOREACH_DRIVER_ON_AUXILIARY_BUS
+ - FOREACH_DRIVER_ON_CDXBUS
+ - FOREACH_DRIVER_ON_PCIBUS
+ - FOREACH_DRIVER_ON_PLATFORM_BUS
+ - FOREACH_DRIVER_ON_UACCEBUS
+ - FOREACH_DRIVER_ON_VMBUS
+ - FOREACH_SUBDEV
+ - FOREACH_SUBDEV_STATE
+ - FOR_EACH
+ - FOR_EACH_BUCKET
+ - FOR_EACH_CNIC_QUEUE
+ - FOR_EACH_COS_IN_TX_QUEUE
+ - FOR_EACH_ETH_QUEUE
+ - FOR_EACH_MEMBER
+ - FOR_EACH_NONDEFAULT_ETH_QUEUE
+ - FOR_EACH_NONDEFAULT_QUEUE
+ - FOR_EACH_PORT
+ - FOR_EACH_PORT_IF
+ - FOR_EACH_QUEUE
+ - FOR_EACH_SUITE_TESTCASE
+ - FOR_EACH_SUITE_TESTSUITE
+ - HLIST_FOR_EACH_ENTRY
+ - ILIST_FOREACH
+ - LIST_FOREACH
+ - LIST_FOREACH_FROM
+ - LIST_FOREACH_FROM_SAFE
+ - LIST_FOREACH_SAFE
+ - LIST_FOR_EACH_ENTRY
+ - LIST_FOR_EACH_ENTRY_SAFE
+ - MLX5_ETH_FOREACH_DEV
+ - MLX5_IPOOL_FOREACH
+ - MLX5_L3T_FOREACH
+ - ML_AVG_FOREACH_QP
+ - ML_AVG_FOREACH_QP_MVTVM
+ - ML_AVG_RESET_FOREACH_QP
+ - ML_MAX_FOREACH_QP
+ - ML_MAX_FOREACH_QP_MVTVM
+ - ML_MAX_RESET_FOREACH_QP
+ - ML_MIN_FOREACH_QP
+ - ML_MIN_FOREACH_QP_MVTVM
+ - ML_MIN_RESET_FOREACH_QP
+ - OSAL_LIST_FOR_EACH_ENTRY
+ - OSAL_LIST_FOR_EACH_ENTRY_SAFE
+ - PLT_TAILQ_FOREACH_SAFE
+ - RTE_BBDEV_FOREACH
+ - RTE_BBDEV_FOREACH
+ - RTE_DEV_FOREACH
+ - RTE_DEV_FOREACH
+ - RTE_DMA_FOREACH_DEV
+ - RTE_DMA_FOREACH_DEV
+ - RTE_EAL_DEVARGS_FOREACH
+ - RTE_EAL_DEVARGS_FOREACH
+ - RTE_ETH_FOREACH_DEV
+ - RTE_ETH_FOREACH_DEV
+ - RTE_ETH_FOREACH_DEV_OF
+ - RTE_ETH_FOREACH_DEV_OF
+ - RTE_ETH_FOREACH_DEV_OWNED_BY
+ - RTE_ETH_FOREACH_DEV_OWNED_BY
+ - RTE_ETH_FOREACH_DEV_SIBLING
+ - RTE_ETH_FOREACH_DEV_SIBLING
+ - RTE_ETH_FOREACH_MATCHING_DEV
+ - RTE_ETH_FOREACH_MATCHING_DEV
+ - RTE_ETH_FOREACH_VALID_DEV
+ - RTE_ETH_FOREACH_VALID_DEV
+ - RTE_GPU_FOREACH
+ - RTE_GPU_FOREACH
+ - RTE_GPU_FOREACH_CHILD
+ - RTE_GPU_FOREACH_CHILD
+ - RTE_GPU_FOREACH_PARENT
+ - RTE_GPU_FOREACH_PARENT
+ - RTE_LCORE_FOREACH
+ - RTE_LCORE_FOREACH
+ - RTE_LCORE_FOREACH_WORKER
+ - RTE_LCORE_FOREACH_WORKER
+ - RTE_TAILQ_FOREACH
+ - RTE_TAILQ_FOREACH
+ - RTE_TAILQ_FOREACH_SAFE
+ - RTE_TAILQ_FOREACH_SAFE
+ - SILIST_FOREACH
+ - SLIST_FOREACH
+ - SLIST_FOREACH_FROM
+ - SLIST_FOREACH_FROM_SAFE
+ - SLIST_FOREACH_PREVPTR
+ - SLIST_FOREACH_SAFE
+ - STAILQ_FOREACH
+ - STAILQ_FOREACH_FROM
+ - STAILQ_FOREACH_FROM_SAFE
+ - STAILQ_FOREACH_SAFE
+ - TAILQ_FOREACH
+ - TAILQ_FOREACH_ENTRY
+ - TAILQ_FOREACH_ENTRY_SAFE
+ - TAILQ_FOREACH_FROM
+ - TAILQ_FOREACH_FROM_SAFE
+ - TAILQ_FOREACH_REVERSE
+ - TAILQ_FOREACH_REVERSE_FROM
+ - TAILQ_FOREACH_REVERSE_FROM_SAFE
+ - TAILQ_FOREACH_REVERSE_SAFE
+ - TAILQ_FOREACH_SAFE
+
+ObjCSpaceAfterProperty: true
+IndentGotoLabels: false
