Introduced through customer's feedback in their attempt to address some
bugs this introduces a memory barrier before posting ctlq tail. This
makes sure memory writes have a chance to take place before HW starts
messing with the descriptors.
Signed-off-by: Soumyadeep Hore <soumyadeep.h...@intel.com>
---
drivers/common/idpf/base/idpf_controlq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/common/idpf/base/idpf_controlq.c
b/drivers/common/idpf/base/idpf_controlq.c
index bd23e54421..ba2e328122 100644
--- a/drivers/common/idpf/base/idpf_controlq.c
+++ b/drivers/common/idpf/base/idpf_controlq.c
@@ -624,6 +624,8 @@ int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw, struct
idpf_ctlq_info *cq,
/* Wrap to end of end ring since current ntp is 0 */
cq->next_to_post = cq->ring_size - 1;
+ idpf_wmb();
+
wr32(hw, cq->reg.tail, cq->next_to_post);
}
--
2.43.0
