On Wed, 4 Sep 2024 11:30:59 +0200 Mattias Rönnblom <hof...@lysator.liu.se> wrote:
> On 2024-09-02 02:39, Varghese, Vipin wrote: > > <snipped> > > > > Thank you Mattias for the comments and question, please let me try to > > explain the same below > > > >> We shouldn't have a separate CPU/cache hierarchy API instead? > > > > Based on the intention to bring in CPU lcores which share same L3 (for > > better cache hits and less noisy neighbor) current API focuses on using > > > > Last Level Cache. But if the suggestion is `there are SoC where L2 cache > > are also shared, and the new API should be provisioned`, I am also > > > > comfortable with the thought. > > > > Rather than some AMD special case API hacked into <rte_lcore.h>, I think > we are better off with no DPDK API at all for this kind of functionality. > > A DPDK CPU/memory hierarchy topology API very much makes sense, but it > should be reasonably generic and complete from the start. Agreed. This one of those cases where the existing project hwloc which is part of open-mpi is more complete and well supported. It supports multiple OS's and can deal with more quirks. https://github.com/open-mpi/hwloc
