On Tue, 8 Oct 2024 07:52:42 +0200 Stanisław Kardach <stanislaw.kard...@gmail.com> wrote:
> On Mon, Oct 7, 2024 at 5:20 PM Stephen Hemminger > <step...@networkplumber.org> wrote: > > > > On Mon, 7 Oct 2024 10:14:22 +0200 > > Stanisław Kardach <stanislaw.kard...@gmail.com> wrote: > > > > > > > > > > > > > > Please do not add more config options via compile flags. > > > > > > It makes it impossible for distros to ship one version. > > > That is a problem with RISC-V in general. Since all features are > > > "extensions" and there is no limit (up to a point) on the permutation > > > of those, we cannot statically build the code for all extensions. > > > Fortunately instructions tend to resolve to nops if an instruction is > > > not present but that still increases the code size for no benefit on > > > platforms without a given extension. > > > > X86 already has the cpu feature flag infrastructure, why not use similar > > mechanism on RiscV? > We can and some further patches I've seen on the list implemented > that. However if that has to be applied in basic intrinsics like > rte_prefetch() which means we'd have to pay a conditional or an > indirect call. It'd be best to test it on a real dataplane platform to > which I don't have access. That makes sense, is there some config file per cpu type like Arm?
