> -----Original Message-----
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Wenzhuo Lu
> Sent: Wednesday, August 26, 2015 3:11 PM
> To: dev at dpdk.org
> Subject: [dpdk-dev] [PATCH] ixgbe: fix a x550 DCB issue
>
> There's a DCB issue on x550. For 8 TCs, if a packet with user priority 6 or 7
> is
> injected to the NIC, then the NIC will put 3 packets into the queue. There's
> also a similar issue for 4 TCs.
> The root cause is RXPBSIZE is not right. RXPBSIZE of x550 is 384. It's
> different
> from other 10G NICs. We need to set the RXPBSIZE according to the NIC type.
>
> Signed-off-by: Wenzhuo Lu <wenzhuo.lu at intel.com>
Acked-by: Jingjing Wu <jingjing.wu at intel.com>
> ---
> drivers/net/ixgbe/ixgbe_rxtx.c | 27 +++++++++++++++++++++++----
> 1 file changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
> index 91023b9..021229f 100644
> --- a/drivers/net/ixgbe/ixgbe_rxtx.c
> +++ b/drivers/net/ixgbe/ixgbe_rxtx.c
> @@ -2915,6 +2915,7 @@ ixgbe_rss_configure(struct rte_eth_dev *dev)
>
> #define NUM_VFTA_REGISTERS 128
> #define NIC_RX_BUFFER_SIZE 0x200
> +#define X550_RX_BUFFER_SIZE 0x180
>
> static void
> ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev) @@ -2943,7 +2944,15
> @@ ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
> * RXPBSIZE
> * split rx buffer up into sections, each for 1 traffic class
> */
> - pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
> + switch (hw->mac.type) {
> + case ixgbe_mac_X550:
> + case ixgbe_mac_X550EM_x:
> + pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
> + break;
> + default:
> + pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
> + break;
> + }
> for (i = 0 ; i < nb_tcs; i++) {
> uint32_t rxpbsize = IXGBE_READ_REG(hw,
> IXGBE_RXPBSIZE(i));
> rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT)); @@ -
> 3317,7 +3326,7 @@ ixgbe_dcb_hw_configure(struct rte_eth_dev *dev, {
> int ret = 0;
> uint8_t i,pfc_en,nb_tcs;
> - uint16_t pbsize;
> + uint16_t pbsize, rx_buffer_size;
> uint8_t config_dcb_rx = 0;
> uint8_t config_dcb_tx = 0;
> uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0}; @@ -3408,9
> +3417,19 @@ ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
> }
> }
>
> + switch (hw->mac.type) {
> + case ixgbe_mac_X550:
> + case ixgbe_mac_X550EM_x:
> + rx_buffer_size = X550_RX_BUFFER_SIZE;
> + break;
> + default:
> + rx_buffer_size = NIC_RX_BUFFER_SIZE;
> + break;
> + }
> +
> if(config_dcb_rx) {
> /* Set RX buffer size */
> - pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
> + pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
> uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
> for (i = 0 ; i < nb_tcs; i++) {
> IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
> @@ -3466,7 +3485,7 @@ ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
>
> /* Check if the PFC is supported */
> if(dev->data->dev_conf.dcb_capability_en &
> ETH_DCB_PFC_SUPPORT) {
> - pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
> + pbsize = (uint16_t) (rx_buffer_size / nb_tcs);
> for (i = 0; i < nb_tcs; i++) {
> /*
> * If the TC count is 8,and the default high_water is 48,
> --
> 1.9.3
