There is the mlx5 NIC limitations - configuring MTU
for PCI Virtual Function has no meaning. The actual maximal
packet size in VF's receiving is limited by MTU configured
on the related PCI Physical Function, the DPDK datapath
running over VF should be prepared to handle packets
of this maximal size.
Signed-off-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
---
doc/guides/nics/mlx5.rst | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 8d1a1311d4..c7dcb74da7 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -191,6 +191,13 @@ Limitations
- IPv4/TCP with CVLAN filtering
- L4 steering rules for port RSS of UDP, TCP and IP
+- PCI Virtual Function MTU:
+
+ Configuring MTU for PCI Virtual Function has no meaning.
+ The actual maximal packet size in VF's receiving is limited by MTU configured
+ on the related PCI Physical Function, the DPDK datapath running over VF
should be
+ prepared to handle packets of this maximal size.
+
- For secondary process:
- Forked secondary process not supported.
--
2.34.1
