>> struct zxdh_hw_internal zxdh_hw_internal[RTE_MAX_ETHPORTS];
>If you want to support primary/secondary in future,
>variables in BSS are not shared between primary and secondary process
This structure mainly registers some PCI ops and
will not be shared between primary/secondary processes.
>> +struct zxdh_shared_data *zxdh_shared_data;
>> +const char *ZXDH_PMD_SHARED_DATA_MZ = "zxdh_pmd_shared_data";
>> +rte_spinlock_t zxdh_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
>> +struct zxdh_dtb_shared_data g_dtb_data;
>The shared data will be a problem if you support multiple devices.
>Or is this really a singleton device with only one bus and slot.
In our latest version, we have optimized by placing this structure in a
private data area
and initializing each device independently.
Can we update later?
>> +static uint32_t
>> +zxdh_np_dtb_soft_init(uint32_t dev_id)
>> +{
>> + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL;
>> +
>> + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id);
>> + if (p_dtb_mgr == NULL) {
>> + p_dpp_dtb_mgr[dev_id] = (ZXDH_DTB_MGR_T
>> *)malloc(sizeof(ZXDH_DTB_MGR_T));
>malloc() returns void *, cast here is not needed.
>Why does DTB_MGR_T come from malloc when most of other data is using
>rte_malloc()?
>
>It will matter if you support multiprocess
I didn't realize it, it was originally intended to use rte_malloc.
Thank you for your comments.
And other issues will modifyed according to the comments.
