The expression "0x1 << 31" is actually undefined since 0x1
is an integer not unsigned. Fix the general problem by using
the existing RTE_BIT32() macros instead.
Shows up as a cryptic warning when building with -Dbsanitize=undefined.
../drivers/net/bnx2x/bnx2x.c:3362:25: error: case label does not reduce to an
integer constant
3362 | case
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
| ^~~~
Signed-off-by: Stephen Hemminger <step...@networkplumber.org>
---
drivers/net/bnx2x/ecore_reg.h | 130 +++++++++++++++++-----------------
1 file changed, 65 insertions(+), 65 deletions(-)
diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h
index 6f7b0522f2..bddea3b832 100644
--- a/drivers/net/bnx2x/ecore_reg.h
+++ b/drivers/net/bnx2x/ecore_reg.h
@@ -4359,71 +4359,71 @@
#define HW_LOCK_RESOURCE_RECOVERY_REG 11
#define HW_LOCK_RESOURCE_RESET 5
#define HW_LOCK_RESOURCE_SPIO 2
-#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1 << 4)
-#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1 << 5)
-#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1 << 19)
-#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1 << 18)
-#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1 << 31)
-#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1 << 30)
-#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1 << 9)
-#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1 << 8)
-#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1 << 7)
-#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1 << 6)
-#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1 << 29)
-#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1 << 28)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1
<< 1)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1
<< 0)
-#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1
<< 18)
-#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1 << 11)
-#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1 << 10)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1 << 13)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1 << 12)
-#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1 << 2)
-#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1 << 12)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1 << 28)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1 << 31)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1 << 29)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1 << 30)
-#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1 << 15)
-#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1 << 14)
-#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1 << 14)
-#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1 << 20)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1 << 31)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1 << 30)
-#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1 << 0)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1
<< 2)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1
<< 3)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1 << 5)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1 << 4)
-#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1 << 3)
-#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1 << 2)
-#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1 << 3)
-#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1 << 2)
-#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1 << 22)
-#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1 << 15)
-#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1 << 27)
-#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1 << 26)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1 << 5)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1 << 4)
-#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1 << 25)
-#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1 << 24)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1
<< 29)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1
<< 28)
-#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1 << 23)
-#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1 << 22)
-#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1 << 27)
-#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1 << 26)
-#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1 << 21)
-#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1 << 20)
-#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1
<< 25)
-#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1
<< 24)
-#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1
<< 16)
-#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1 << 9)
-#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1 << 8)
-#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1 << 7)
-#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1 << 6)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1
<< 11)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1
<< 10)
+#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT RTE_BIT32(4)
+#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR RTE_BIT32(5)
+#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT RTE_BIT32(19)
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR RTE_BIT32(18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT RTE_BIT32(31)
+#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR RTE_BIT32(30)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT RTE_BIT32(9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR RTE_BIT32(8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT RTE_BIT32(7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR RTE_BIT32(6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT RTE_BIT32(29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR RTE_BIT32(28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT
RTE_BIT32(1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
RTE_BIT32(0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
RTE_BIT32(18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT RTE_BIT32(11)
+#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR RTE_BIT32(10)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT RTE_BIT32(13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR RTE_BIT32(12)
+#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 RTE_BIT32(2)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR RTE_BIT32(12)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY RTE_BIT32(28)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY RTE_BIT32(31)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY RTE_BIT32(29)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY RTE_BIT32(30)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT RTE_BIT32(15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR RTE_BIT32(14)
+#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR RTE_BIT32(14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR RTE_BIT32(20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT RTE_BIT32(31)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR RTE_BIT32(30)
+#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR RTE_BIT32(0)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
RTE_BIT32(2)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
RTE_BIT32(3)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT RTE_BIT32(5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR RTE_BIT32(4)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT RTE_BIT32(3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR RTE_BIT32(2)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT RTE_BIT32(3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR RTE_BIT32(2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR RTE_BIT32(22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5 RTE_BIT32(15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT RTE_BIT32(27)
+#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR RTE_BIT32(26)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT RTE_BIT32(5)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR RTE_BIT32(4)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT RTE_BIT32(25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR RTE_BIT32(24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT
RTE_BIT32(29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
RTE_BIT32(28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT RTE_BIT32(23)
+#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR RTE_BIT32(22)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT RTE_BIT32(27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR RTE_BIT32(26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT RTE_BIT32(21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR RTE_BIT32(20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT
RTE_BIT32(25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
RTE_BIT32(24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
RTE_BIT32(16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT RTE_BIT32(9)
+#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR RTE_BIT32(8)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT RTE_BIT32(7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR RTE_BIT32(6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT
RTE_BIT32(11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
RTE_BIT32(10)
#define RESERVED_GENERAL_ATTENTION_BIT_0 0
#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
--
2.45.2
