On Mon, Oct 27, 2025 at 02:28:00PM -0400, Soumyadeep Hore wrote:
> On enabling TxPP PTP clock was getting corrupted as timesync was enabled
> on during setup. Currently timesync will be enabled during start of tx
> queue, hence enabling PHC clock to get updated on starting and stopping
> of ports.
Can you clarify in a bit more detail, how did enabling the timesync during
setup corrupt the clock, and how does enabling it only on start fix it?
>
> Fixes: 0b6ff09a1f19 ("net/intel: support Tx packet pacing for E830")
> Cc: [email protected]
>
> Signed-off-by: Soumyadeep Hore <[email protected]>
> ---
> drivers/net/intel/ice/ice_rxtx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/intel/ice/ice_rxtx.c
> b/drivers/net/intel/ice/ice_rxtx.c
> index 33d82cd46d..7473d45260 100644
> --- a/drivers/net/intel/ice/ice_rxtx.c
> +++ b/drivers/net/intel/ice/ice_rxtx.c
> @@ -908,6 +908,7 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t
> tx_queue_id)
> rte_free(txq_elem);
> return err;
> }
> + dev->dev_ops->timesync_enable(dev);
> } else {
> txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
>
> @@ -1671,7 +1672,6 @@ ice_tx_queue_setup(struct rte_eth_dev *dev,
> PMD_INIT_LOG(ERR, "Cannot register Tx mbuf field/flag
> for timestamp");
> return -EINVAL;
> }
> - dev->dev_ops->timesync_enable(dev);
>
> txq->tsq->nb_ts_desc =
> ice_calc_ts_ring_count(ICE_VSI_TO_HW(vsi), txq->nb_tx_desc);
> ring_size = sizeof(struct ice_ts_desc) * txq->tsq->nb_ts_desc;
> --
> 2.47.1
>
