Change eth_igc_read_clock() to read from hardware timestamp registers
(E1000_SYSTIML/E1000_SYSTIMH) instead of using system clock_gettime().
This ensures that the clock reading is consistent with the hardware's
internal time base used for Qbv cycle and launch time scheduling,
providing better accuracy for Time-Sensitive Networking applications.
Fixes: 9630f7c71ecd ("net/igc: enable launch time offloading")
Cc: [email protected]
Signed-off-by: David Zage <[email protected]>
Signed-off-by: Song Yoong Siang <[email protected]>
---
v1:
https://patches.dpdk.org/project/dpdk/patch/[email protected]/
changelog:
v1 -> v2
- reuse the existing eth_igc_timesync_read_time() (Soumyadeep).
---
drivers/net/intel/e1000/igc_ethdev.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/intel/e1000/igc_ethdev.c
b/drivers/net/intel/e1000/igc_ethdev.c
index b9c91d2446..d4edc82668 100644
--- a/drivers/net/intel/e1000/igc_ethdev.c
+++ b/drivers/net/intel/e1000/igc_ethdev.c
@@ -2813,6 +2813,12 @@ eth_igc_timesync_read_time(struct rte_eth_dev *dev,
struct timespec *ts)
{
struct e1000_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ /*
+ * Reading the SYSTIML register latches the upper 32 bits to the SYSTIMH
+ * shadow register for coherent access. As long as we read SYSTIML first
+ * followed by SYSTIMH, we avoid race conditions where the time rolls
+ * over between the two register reads.
+ */
ts->tv_nsec = E1000_READ_REG(hw, E1000_SYSTIML);
ts->tv_sec = E1000_READ_REG(hw, E1000_SYSTIMH);
@@ -2972,10 +2978,10 @@ eth_igc_timesync_disable(struct rte_eth_dev *dev)
static int
eth_igc_read_clock(__rte_unused struct rte_eth_dev *dev, uint64_t *clock)
{
- struct timespec system_time;
+ struct timespec ts;
- clock_gettime(CLOCK_REALTIME, &system_time);
- *clock = system_time.tv_sec * NSEC_PER_SEC + system_time.tv_nsec;
+ eth_igc_timesync_read_time(dev, &ts);
+ *clock = rte_timespec_to_ns(&ts);
return 0;
}
--
2.48.1
