Hi,
On 21/01/2026 10:14 AM, Shani Peretz wrote:
When compiling with optimizations, the compiler uses AVX-512
instructions (vmovdqa64) to efficiently zero large structures.
This instruction requires 64-byte aligned memory addresses.
When compiling with ASAN, the stack layout is modified for
instrumentation, which can break the 64-byte alignment of
local structures. This causes a segfault when the misaligned
vmovdqa64 instruction executes.
Fix by adding MLX5DR_ASAN_ALIGN macro to ensure 64-byte alignment
when building with ASan.
Fixes: 338aaf911665 ("net/mlx5/hws: add send FW match STE using gen WQE")
Fixes: 12802ab2c8e2 ("net/mlx5/hws: support GTA WQE write using FW command")
Fixes: 405242c52dd5 ("net/mlx5/hws: add rule object")
Cc: [email protected]
Signed-off-by: Shani Peretz <[email protected]>
Acked-by: Bing Zhao <[email protected]>
Patch applied to next-net-mlx,
Kindest regards
Raslan Darawsheh
