On Fri, Aug 28, 2026 at 09:32:52PM +0100, Yonghao Li wrote:
> LZCNT support is enumerated by CPUID.80000001H:ECX[5]. The current
> definition checks ECX bit 4, which identifies CR8 legacy mode on AMD
> processors and is reserved on Intel processors. As a result,
> RTE_CPUFLAG_LZCNT can be reported incorrectly.
>
> Check ECX bit 5 instead.
>
> Fixes: af75078fece3 ("first public release")
> Cc: [email protected]
> Signed-off-by: Yonghao Li <[email protected]>
> ---
> .mailmap | 1 +
> lib/eal/x86/rte_cpuflags.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/.mailmap b/.mailmap
> index fcb3d1bb3f..fad671fbe9 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -1933,6 +1933,7 @@ Yong Wang <[email protected]> <[email protected]>
> Yong Xu <[email protected]>
> Yong Zhang <[email protected]>
> Yongfeng Wang <[email protected]>
> +Yonghao Li <[email protected]>
> Yongji Xie <[email protected]>
> Yongjie Gu <[email protected]>
> Yongping Zhang <[email protected]>
> diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
> index 5d1f352e04..80b71a3ce0 100644
> --- a/lib/eal/x86/rte_cpuflags.c
> +++ b/lib/eal/x86/rte_cpuflags.c
> @@ -137,7 +137,7 @@ struct feature_entry rte_cpu_feature_table[] = {
> FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
>
> FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)
> - FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)
> + FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 5)
> FEAT_DEF(MONITORX, 0x80000001, 0, RTE_REG_ECX, 29)
>
Confirmed by checking Table 21-90 in the Intel SDM Vol 1 docs. Thanks for
catching this.
Acked-by: Bruce Richardson <[email protected]>
