The interrupt throttling register(ITR) bank 0 value is set to 2, but to ensure best performance across all systems also set the bank 1 value to match.
Signed-off-by: Bruce Richardson <[email protected]> --- drivers/net/intel/iavf/iavf_ethdev.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/intel/iavf/iavf_ethdev.c b/drivers/net/intel/iavf/iavf_ethdev.c index a8abe0154c..dc3cea0b95 100644 --- a/drivers/net/intel/iavf/iavf_ethdev.c +++ b/drivers/net/intel/iavf/iavf_ethdev.c @@ -899,10 +899,7 @@ static int iavf_config_rx_queues_irqs(struct rte_eth_dev *dev, (0 << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | (2UL << IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT)); - /* debug - check for success! the return value - * should be 2, offset is 0x2800 - */ - /* IAVF_READ_REG(hw, IAVF_VFINT_ITRN1(0, 0)); */ + IAVF_WRITE_REG(hw, IAVF_VFINT_ITRN1(1, vf->msix_base - 1), 2); } else { /* If no WB_ON_ITR offload flags, need to set * interrupt for descriptor write back. -- 2.53.0
