Hello, On Fri, 10 Jul 2026 at 09:36, Raghavendra Ningoji <[email protected]> wrote: > > This series adds a new dmadev poll-mode driver for the AMD AE4DMA > hardware DMA engine, split into introduction, control path and data > path patches, plus a small dmadev test-suite patch. > > v5 addresses the v4 review comments from Chengwen Feng. > > Changes since v4: > > Patch 1/4 (introduce): > - Drop the custom AE4DMA_BIT() macro and use RTE_BIT32() from > rte_bitops.h for the DWORD0 control-bit and memory-type defines. > - Remove the now-unused per-queue status[] array from > struct ae4dma_cmd_queue (completion status is derived directly from > the descriptors in patch 3). > > Patch 3/4 (data path): > - Fix rte_dma_completed(): stop at the first failed descriptor and > return only the run of successful ops preceding it, set *has_error, > and leave the failed op to be reported by rte_dma_completed_status(). > last_idx now reports the last successfully completed ring_idx. > - Drop the redundant 'if (last_idx != NULL)' check; the framework > always passes a non-NULL last_idx. > > Patch 4/4 (test): > - Unchanged; retains TEST_SKIPPED for sub-32 burst capacity. > > Changes since v3 (carried over, for reference): > > Patch 1/4 (introduce): > - Fix copyright years (2025/2024 -> 2026) in ae4dma.rst and meson.build. > - Drop the unnecessary memzone lookup/reuse logic; rings are reserved > once at probe. > - Trim ae4dma_hw_defs.h includes; move the rest to ae4dma_internal.h. > - Remove redundant double blank lines in ae4dma_internal.h. > - Use an initialiser instead of memset() for hwq_dev_name and reorder > local declarations in descending length. > - Make the probe-failure log message more descriptive. > - Build only on Linux (add the is_linux guard to meson.build). > - Add a hw_base field to anchor the free-running ring index. > > Patch 2/4 (control path): > - Advertise RTE_DMA_CAPA_OPS_COPY in dev_info_get. > - Use 'conf_sz < sizeof(...)' instead of '!=' to stay ABI compatible. > - Drop checks already performed by the dmadev framework. > - Reset the free-running ring indices in vchan_setup and dev_start, > anchoring index 0 to the current HW consumer slot (hw_base). > - Reword the commit log for the 2 to 32 descriptor range. > > Patch 3/4 (data path): > - Return free-running 16-bit ring_idx values from rte_dma_copy() and > completed()/completed_status(); HW slot = (hw_base + idx) & mask. > - Map the AE4DMA alignment error to RTE_DMA_STATUS_ERROR_UNKNOWN. > - Drop the redundant power-of-two/range check in burst_capacity(). > - Document the 32-descriptor / 31-outstanding ring-depth limitation. > > Patch 4/4 (test) - added in v4: > - Return TEST_SKIPPED instead of failing the instance suite when a > device reports burst capacity below 32, matching the existing < 64 > skip used by the burst_capacity test. > > Note: the power-of-two rounding of nb_desc in vchan_setup is retained > on purpose: the free-running ring index is mapped to a HW ring slot by > masking, which is only correct for a power-of-two depth. > > Raghavendra Ningoji (4): > dma/ae4dma: introduce AMD AE4DMA DMA PMD > dma/ae4dma: add control path operations > dma/ae4dma: add data path operations > test/dma: skip instance suite on low burst capacity > > .mailmap | 1 + > MAINTAINERS | 5 + > app/test/test_dmadev.c | 8 +- > doc/guides/dmadevs/ae4dma.rst | 77 +++ > doc/guides/dmadevs/index.rst | 1 + > doc/guides/rel_notes/release_26_07.rst | 7 + > drivers/dma/ae4dma/ae4dma_dmadev.c | 677 +++++++++++++++++++++++++ > drivers/dma/ae4dma/ae4dma_hw_defs.h | 149 ++++++ > drivers/dma/ae4dma/ae4dma_internal.h | 113 +++++ > drivers/dma/ae4dma/meson.build | 13 + > drivers/dma/meson.build | 1 + > usertools/dpdk-devbind.py | 5 +- > 12 files changed, 1054 insertions(+), 3 deletions(-) > create mode 100644 doc/guides/dmadevs/ae4dma.rst > create mode 100644 drivers/dma/ae4dma/ae4dma_dmadev.c > create mode 100644 drivers/dma/ae4dma/ae4dma_hw_defs.h > create mode 100644 drivers/dma/ae4dma/ae4dma_internal.h > create mode 100644 drivers/dma/ae4dma/meson.build
Rebased on top of v26.11-rc0, and recent cleanup: https://patchwork.dpdk.org/project/dpdk/patch/[email protected]/ I fixed a few coding style issues. Series applied. Thanks to Chengwen Feng for the reviews. AI reported a few (minor) issues, please have a look and send followup patches if those issues are confirmed. . **HW queue enabled but base address programmed afterward** In `ae4dma_add_queue()`: ```c AE4DMA_WRITE_REG(&cmd_q->hwq_regs->control_reg.control_raw, AE4DMA_CMD_QUEUE_ENABLE); ... AE4DMA_WRITE_REG(&cmd_q->hwq_regs->qbase_lo, dma_addr_lo); AE4DMA_WRITE_REG(&cmd_q->hwq_regs->qbase_hi, dma_addr_hi); ``` The queue is enabled before the base address is programmed. If the hardware starts processing before the base address is set, it could read from an undefined location. The queue should be enabled **after** programming the base address. . **`qbase_desc` cast drops const qualifier** In `ae4dma_add_queue()`: ```c cmd_q->qbase_desc = q_mz->addr; ``` `q_mz->addr` is `void *` (mutable), but this is aliased with `qbase_addr` pointing to the same location. The descriptor ring should be zero-initialized before use if the hardware expects valid initial descriptor state. . **Typo: MEMEORY** ```c #define AE4DMA_DWORD0_SOURCE_MEMEORY_TYPE RTE_GENMASK64(7, 6) #define AE4DMA_DWORD0_SOURCE_MEMEORY_TYPE_MEMORY (0x0) #define AE4DMA_DWORD0_SOURCE_MEMEORY_TYPE_IOMEMORY RTE_BIT32(6) ``` "MEMEORY" should be "MEMORY". . **`RTE_GENMASK64` used for 8-bit masks** ```c #define AE4DMA_DWORD0_DESTINATION_MEMORY_TYPE RTE_GENMASK64(5, 4) #define AE4DMA_DWORD0_SOURCE_MEMEORY_TYPE RTE_GENMASK64(7, 6) ``` These masks are for bits 4-5 and 6-7 of an 8-bit field. `RTE_GENMASK32` would be more appropriate for 32-bit register fields. . **Potential NULL pointer dereference in `ae4dma_dev_start()`** (lines 82-93) The function dereferences `cmd_q->hwq_regs` without checking if it is NULL. While `ae4dma_dev_stop()` and `ae4dma_vchan_status()` correctly check `cmd_q->hwq_regs != NULL` before dereferencing, `ae4dma_dev_start()` does not. If `dev_start()` is called before the queue is properly initialized via `ae4dma_add_queue()`, this will cause a crash. ```c static int ae4dma_dev_start(struct rte_dma_dev *dev) { ... /* No NULL check before these dereferences */ AE4DMA_WRITE_REG(&cmd_q->hwq_regs->max_idx, nb); AE4DMA_WRITE_REG(&cmd_q->hwq_regs->control_reg.control_raw, AE4DMA_CMD_QUEUE_ENABLE); ... hw_pos = (uint16_t)(AE4DMA_READ_REG(&cmd_q->hwq_regs->read_idx) & (nb - 1)); ``` **Suggested fix**: Add a NULL check at the start of `ae4dma_dev_start()`: ```c if (cmd_q->hwq_regs == NULL) return -EINVAL; ``` . **Mismatched brace placement in `ae4dma_dev_dump()`** The output includes `fprintf(f, " }\n");` that doesn't have a corresponding opening brace in the output, creating confusing debug output. -- David Marchand
