ice_ptp_tmr_cmd() prepares the source timer, then the PHY ports, and
then starts the command with a write to GLTSYN_CMD_SYNC. For E830,
ice_ptp_port_cmd_e830() writes the command to E830_ETH_GLTSYN_CMD with
a sideband queue message. E810 and E830 have no sideband queue, so the
message goes to firmware on the admin queue as a neighbor device
request. The firmware rejects it with ICE_ERR_AQ_ERROR (-100).
E830 has an internal PHY, and its port timers follow the source timer.
On E830, ice_ptp_init_time() and ice_ptp_write_incval() write only the
source timer, and ice_ptp_adj_clock() prepares no PHY adjustment.
Also, E830_ETH_GLTSYN_CMD (0x00088814) is the address of
GLTSYN_CMD_SYNC, and the only command that gets to this function,
ADJ_TIME (0x04), leaves the SYNC field of that register at 0.
Do not prepare a port command on E830, and remove the unused
function and register define.
Before commit f9767f70cb73 ("net/ice/base: fix adjust timer
programming for E830"), ice_ptp_adj_clock() returned early on E830,
and nothing called ice_ptp_port_cmd_e830(). Since that commit,
each rte_eth_timesync_adjust_time() with a delta in the 32-bit range
fails with "PTP adj clock failed, err -100", and the PHC does not
change. A PTP client then cannot discipline the clock.
Fixes: 881169950d80 ("net/ice/base: implement initial PTP support for E830")
Fixes: f9767f70cb73 ("net/ice/base: fix adjust timer programming for E830")
Cc: [email protected]
Signed-off-by: Marek Kasiewicz <[email protected]>
Signed-off-by: Dawid Wesierski <[email protected]>
---
Tested on an E830-CC PF (firmware 1.3833.0) with a program that calls
rte_eth_timesync_adjust_time() after rte_eth_timesync_enable(). "step" is
the change of PHC minus CLOCK_REALTIME across the call; with a delta of 0
it is about -245 ns, the cost of the reads.
delta (ns) without the patch with the patch
0 -1, "err -100" 0, step -238 to -249 ns
+1000 - 0, step +691 to +890 ns (3 runs)
-1000 - 0, step -1128 to -1250 ns (3 runs)
+1000000 -1, step -1279 ns 0, step +999762 ns
-1000000 -1, step -171 ns 0, step -1000247 ns
drivers/net/intel/ice/base/ice_ptp_hw.c | 22 ++--------------------
drivers/net/intel/ice/base/ice_ptp_hw.h | 2 --
2 files changed, 2 insertions(+), 22 deletions(-)
diff --git a/drivers/net/intel/ice/base/ice_ptp_hw.c
b/drivers/net/intel/ice/base/ice_ptp_hw.c
index 5688f969ce..84b2486c49 100644
--- a/drivers/net/intel/ice/base/ice_ptp_hw.c
+++ b/drivers/net/intel/ice/base/ice_ptp_hw.c
@@ -5612,25 +5612,6 @@ ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw,
u64 time)
return 0;
}
-/**
- * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
- * @hw: pointer to HW struct
- * @cmd: Command to be sent to the port
- * @lock_sbq: true if the sideband queue lock must be acquired
- *
- * Prepare the external PHYs connected to this device for a timer sync
- * command.
- */
-static int
-ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
- bool lock_sbq)
-{
- u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
-
- return ice_write_phy_reg_e810_lp(hw, E830_ETH_GLTSYN_CMD, val,
- lock_sbq);
-}
-
/**
* ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY
* @hw: pointer to the HW struct
@@ -5881,7 +5862,8 @@ static int ice_ptp_port_cmd(struct ice_hw *hw, enum
ice_ptp_tmr_cmd cmd,
/* PHY models which can program all ports simultaneously */
switch (hw->phy_model) {
case ICE_PHY_E830:
- return ice_ptp_port_cmd_e830(hw, cmd, lock_sbq);
+ /* The internal PHY follows the source timer command */
+ return 0;
case ICE_PHY_E810:
return ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
default:
diff --git a/drivers/net/intel/ice/base/ice_ptp_hw.h
b/drivers/net/intel/ice/base/ice_ptp_hw.h
index 534e05a8dd..31cbcc39d0 100644
--- a/drivers/net/intel/ice/base/ice_ptp_hw.h
+++ b/drivers/net/intel/ice/base/ice_ptp_hw.h
@@ -617,8 +617,6 @@ ice_get_base_incval(struct ice_hw *hw, enum
ice_src_tmr_mode src_tmr_mode)
/* E810 timer command register */
#define E810_ETH_GLTSYN_CMD 0x03000344
-/* E830 timer command register */
-#define E830_ETH_GLTSYN_CMD 0x00088814
/* Source timer incval macros */
#define INCVAL_HIGH_M 0xFF
base-commit: cc048a01ec4c7ae5f63a6607260ac05cc1588968
prerequisite-patch-id: 7f8d7046d07c815969a50ef60697c6c779bcbaa8
--
2.43.0
---------------------------------------------------------------------
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