Include vfio map/rd/wr support for pci ioport. Signed-off-by: Santosh Shukla <sshukla at mvista.com> Acked-by: Anatoly Burakov <anatoly.burakov at intel.com> Acked-by: David Marchand <david.marchand at 6wind.com> --- v7: - This is enhancement patch for vfio map/rd/wr, rebased on top of David(s) - "Rework ioport for virtio" patchset. For more information about api, refer patch [1]. [1] http://dpdk.org/dev/patchwork/patch/10426/
v8: - Remove rte_pci_ioport malloc and rte_free()/unmap() func from v7. - removed umap from git header. v9: - renamed p->offset to p->base lib/librte_eal/linuxapp/eal/eal_pci_vfio.c | 36 ++++++++++++++++++---------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c b/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c index 4832313..4d29a0d 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c @@ -74,6 +74,7 @@ EAL_REGISTER_TAILQ(rte_vfio_tailq) #define VFIO_GROUP_FMT "/dev/vfio/%u" #define VFIO_NOIOMMU_GROUP_FMT "/dev/vfio/noiommu-%u" #define VFIO_GET_REGION_ADDR(x) ((uint64_t) x << 40ULL) +#define VFIO_GET_REGION_IDX(x) (x >> 40) /* per-process VFIO config */ static struct vfio_config vfio_cfg; @@ -999,30 +1000,41 @@ int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar, struct rte_pci_ioport *p) { - RTE_SET_USED(dev); - RTE_SET_USED(bar); - RTE_SET_USED(p); - return -1; + if (bar < VFIO_PCI_BAR0_REGION_INDEX || + bar > VFIO_PCI_BAR5_REGION_INDEX) { + RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar); + return -1; + } + + p->dev = dev; + p->base = VFIO_GET_REGION_ADDR(bar); + return 0; } void pci_vfio_ioport_read(struct rte_pci_ioport *p, void *data, size_t len, off_t offset) { - RTE_SET_USED(p); - RTE_SET_USED(data); - RTE_SET_USED(len); - RTE_SET_USED(offset); + const struct rte_intr_handle *intr_handle = &p->dev->intr_handle; + + if (pread64(intr_handle->vfio_dev_fd, data, + len, p->base + offset) <= 0) + RTE_LOG(ERR, EAL, + "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n", + VFIO_GET_REGION_IDX(p->base), (int)offset); } void pci_vfio_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset) { - RTE_SET_USED(p); - RTE_SET_USED(data); - RTE_SET_USED(len); - RTE_SET_USED(offset); + const struct rte_intr_handle *intr_handle = &p->dev->intr_handle; + + if (pwrite64(intr_handle->vfio_dev_fd, data, + len, p->base + offset) <= 0) + RTE_LOG(ERR, EAL, + "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n", + VFIO_GET_REGION_IDX(p->base), (int)offset); } int -- 1.7.9.5