It adds the setting VLAN ether type of single VLAN, inner and outer VLAN. Single VLAN is treated as inner VLAN as usual.
Signed-off-by: Helin Zhang <helin.zhang at intel.com> --- drivers/net/i40e/i40e_ethdev.c | 68 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 4 deletions(-) v2: - Used RTE_NEXT_ABI to avoid ABI change issue. diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 1da5690..a5b9289 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -273,6 +273,11 @@ #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL +#define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) +#define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 +#define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ + I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) + static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev); static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -2324,13 +2329,58 @@ i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) } static void -i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev, +i40e_vlan_tpid_set(struct rte_eth_dev *dev, #ifdef RTE_NEXT_ABI - __rte_unused enum rte_vlan_type vlan_type, + enum rte_vlan_type vlan_type, #endif - __rte_unused uint16_t tpid) + uint16_t tpid) { - PMD_INIT_FUNC_TRACE(); + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint64_t reg_r = 0, reg_w = 0; + uint16_t reg_id = 0; + int ret; + +#ifdef RTE_NEXT_ABI + switch (vlan_type) { + case ETH_VLAN_TYPE_OUTER: + reg_id = 2; + break; + case ETH_VLAN_TYPE_INNER: + reg_id = 3; + break; + default: + PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type); + return; + } +#else + reg_id = 3; +#endif /* RTE_NEXT_ABI */ + + ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), + ®_r, NULL); + if (ret != I40E_SUCCESS) { + PMD_DRV_LOG(ERR, "Fail to debug read from " + "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id); + return; + } + PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: " + "0x%08"PRIx64"", reg_id, reg_r); + + reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK)); + reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT); + if (reg_r == reg_w) { + PMD_DRV_LOG(DEBUG, "No need to write"); + return; + } + ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), + reg_w, NULL); + if (ret != I40E_SUCCESS) { + PMD_DRV_LOG(ERR, "Fail to debug write to " + "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id); + return; + } + PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to " + "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id); } static void @@ -7345,11 +7395,21 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, static void i40e_hw_init(struct i40e_hw *hw) { + struct rte_eth_dev *dev = ((struct i40e_adapter *)(hw->back))->eth_dev; + /* clear the PF Queue Filter control register */ I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); /* Disable symmetric hash per port */ i40e_set_symmetric_hash_enable_per_port(hw, 0); + + /* Set the global registers with default ether type value */ +#ifdef RTE_NEXT_ABI + i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN); + i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN); +#else + i40e_vlan_tpid_set(dev, ETHER_TYPE_VLAN); +#endif /* RTE_NEXT_ABI */ } enum i40e_filter_pctype -- 2.5.0