[dpdk-dev] [PATCH v4 13/32] net/qede/base: comment enhancements

Tue, 18 Oct 2016 21:11:27 -0700 

Comment additions and modifications

Signed-off-by: Rasesh Mody <rasesh.mody at qlogic.com>
---
 drivers/net/qede/base/ecore_dev_api.h      |   4 +-
 drivers/net/qede/base/ecore_gtt_reg_addr.h |  10 +
 drivers/net/qede/base/ecore_hsi_common.h   | 863 +++++++++++++++++++---------
 drivers/net/qede/base/ecore_hsi_eth.h      | 877 ++++++++++++++++++++++-------
 drivers/net/qede/base/ecore_hw_defs.h      |  33 +-
 drivers/net/qede/base/ecore_init_ops.h     |   6 +-
 drivers/net/qede/base/ecore_mcp.h          |  31 +-
 drivers/net/qede/base/ecore_sp_api.h       |   5 +-
 drivers/net/qede/base/eth_common.h         | 154 +++--
 drivers/net/qede/base/mcp_public.h         |  99 +++-
 10 files changed, 1519 insertions(+), 563 deletions(-)

diff --git a/drivers/net/qede/base/ecore_dev_api.h 
b/drivers/net/qede/base/ecore_dev_api.h
index e6924bd..1a810b5 100644
--- a/drivers/net/qede/base/ecore_dev_api.h
+++ b/drivers/net/qede/base/ecore_dev_api.h
@@ -98,8 +98,8 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev);

 /**
  * @brief ecore_hw_stop_fastpath -should be called incase
- *        slowpath is still required for the device, but
- *        fastpath is not.
+ *        slowpath is still required for the device,
+ *        but fastpath is not.
  *
  * @param p_dev
  *
diff --git a/drivers/net/qede/base/ecore_gtt_reg_addr.h 
b/drivers/net/qede/base/ecore_gtt_reg_addr.h
index 0eba1aa..6395b7c 100644
--- a/drivers/net/qede/base/ecore_gtt_reg_addr.h
+++ b/drivers/net/qede/base/ecore_gtt_reg_addr.h
@@ -10,33 +10,43 @@
 #define GTT_REG_ADDR_H

 /* Win 2 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_IGU_CMD                                      
0x00f000UL

 /* Win 3 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_TSDM_RAM                                     
0x010000UL

 /* Win 4 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_MSDM_RAM                                     
0x011000UL

 /* Win 5 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024                                
0x012000UL

 /* Win 6 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_USDM_RAM                                     
0x013000UL

 /* Win 7 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_USDM_RAM_1024                                
0x014000UL

 /* Win 8 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_USDM_RAM_2048                                
0x015000UL

 /* Win 9 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_XSDM_RAM                                     
0x016000UL

 /* Win 10 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_YSDM_RAM                                     
0x017000UL

 /* Win 11 */
+/* Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2 */
 #define GTT_BAR0_MAP_REG_PSDM_RAM                                     
0x018000UL

 #endif
diff --git a/drivers/net/qede/base/ecore_hsi_common.h 
b/drivers/net/qede/base/ecore_hsi_common.h
index 3c4d7c0..179d410 100644
--- a/drivers/net/qede/base/ecore_hsi_common.h
+++ b/drivers/net/qede/base/ecore_hsi_common.h
@@ -13,6 +13,7 @@
 /********************************/
 #include "common_hsi.h"

+
 /*
  * opcodes for the event ring
  */
@@ -30,6 +31,7 @@ enum common_event_opcode {
        MAX_COMMON_EVENT_OPCODE
 };

+
 /*
  * Common Ramrod Command IDs
  */
@@ -45,6 +47,7 @@ enum common_ramrod_cmd_id {
        MAX_COMMON_RAMROD_CMD_ID
 };

+
 /*
  * The core storm context for the Ystorm
  */
@@ -65,8 +68,8 @@ struct pstorm_core_conn_st_ctx {
 struct xstorm_core_conn_st_ctx {
        __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
        __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
-       struct regpair consolid_base_addr /* Consolidation Ring Base Address */
-         ;
+/* Consolidation Ring Base Address */
+       struct regpair consolid_base_addr;
        __le16 spq_cons /* SPQ Ring Consumer */;
        __le16 consolid_cons /* Consolidation Ring Consumer */;
        __le32 reserved0[55] /* Pad to 15 cycles */;
@@ -76,210 +79,300 @@ struct xstorm_core_conn_ag_ctx {
        u8 reserved0 /* cdu_validation */;
        u8 core_state /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT        0
+/* exist_in_qm1 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT           1
+/* exist_in_qm2 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT           2
+/* exist_in_qm3 */
 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT        3
+/* bit4 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT           4
+/* cf_array_active */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT           5
+/* bit6 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT           6
+/* bit7 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT           7
        u8 flags1;
+/* bit8 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT           0
+/* bit9 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT           1
+/* bit10 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK            0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT           2
+/* bit11 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT               3
+/* bit12 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT               4
+/* bit13 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT               5
+/* bit14 */
 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK       0x1
 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT      6
+/* bit15 */
 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT        7
        u8 flags2;
+/* timer0cf */
 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK                  0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT                 0
+/* timer1cf */
 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK                  0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT                 2
+/* timer2cf */
 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK                  0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT                 4
+/* timer_stop_all */
 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK                  0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT                 6
        u8 flags3;
-#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK                  0x3
+#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK                  0x3 /* cf4 */
 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT                 0
-#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK                  0x3
+#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK                  0x3 /* cf5 */
 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT                 2
-#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK                  0x3
+#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK                  0x3 /* cf6 */
 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT                 4
-#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK                  0x3
+#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK                  0x3 /* cf7 */
 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT                 6
        u8 flags4;
-#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK                  0x3
+#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK                  0x3 /* cf8 */
 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT                 0
-#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK                  0x3
+#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK                  0x3 /* cf9 */
 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT                 2
+/* cf10 */
 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT                4
+/* cf11 */
 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT                6
        u8 flags5;
+/* cf12 */
 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT                0
+/* cf13 */
 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT                2
+/* cf14 */
 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT                4
+/* cf15 */
 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT                6
        u8 flags6;
+/* cf16 */
 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK     0x3
 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT    0
+/* cf_array_cf */
 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                2
+/* cf18 */
 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                0x3
 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT               4
+/* cf19 */
 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK         0x3
 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT        6
        u8 flags7;
+/* cf20 */
 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK             0x3
 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT            0
+/* cf21 */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK           0x3
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT          2
+/* cf22 */
 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK            0x3
 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT           4
+/* cf0en */
 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT               6
+/* cf1en */
 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT               7
        u8 flags8;
+/* cf2en */
 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT               0
+/* cf3en */
 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT               1
+/* cf4en */
 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT               2
+/* cf5en */
 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT               3
+/* cf6en */
 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT               4
+/* cf7en */
 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT               5
+/* cf8en */
 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT               6
+/* cf9en */
 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT               7
        u8 flags9;
+/* cf10en */
 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT              0
+/* cf11en */
 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT              1
+/* cf12en */
 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT              2
+/* cf13en */
 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT              3
+/* cf14en */
 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT              4
+/* cf15en */
 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT              5
+/* cf16en */
 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK  0x1
 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
+/* cf_array_cf_en */
 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT              7
        u8 flags10;
+/* cf18en */
 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT            0
+/* cf19en */
 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK      0x1
 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT     1
+/* cf20en */
 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK          0x1
 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT         2
+/* cf21en */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK           0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT          3
+/* cf22en */
 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT        4
+/* cf23en */
 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK               0x1
 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT              5
+/* rule0en */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK           0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT          6
+/* rule1en */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK           0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT          7
        u8 flags11;
+/* rule2en */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK           0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT          0
+/* rule3en */
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK           0x1
 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT          1
+/* rule4en */
 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK       0x1
 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT      2
+/* rule5en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK              0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT             3
+/* rule6en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK              0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT             4
+/* rule7en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK              0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT             5
+/* rule8en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT        6
+/* rule9en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK              0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT             7
        u8 flags12;
+/* rule10en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT            0
+/* rule11en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT            1
+/* rule12en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT        2
+/* rule13en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT        3
+/* rule14en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT            4
+/* rule15en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT            5
+/* rule16en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT            6
+/* rule17en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT            7
        u8 flags13;
+/* rule18en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT            0
+/* rule19en */
 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK             0x1
 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT            1
+/* rule20en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT        2
+/* rule21en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT        3
+/* rule22en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT        4
+/* rule23en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT        5
+/* rule24en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT        6
+/* rule25en */
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK         0x1
 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT        7
        u8 flags14;
+/* bit16 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT               0
+/* bit17 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT               1
+/* bit18 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT               2
+/* bit19 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT               3
+/* bit20 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT               4
+/* bit21 */
 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK                0x1
 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT               5
+/* cf23 */
 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK                 0x3
 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT                6
        u8 byte2 /* byte2 */;
@@ -339,84 +432,84 @@ struct tstorm_core_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
-#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1
+#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
-#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1
+#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
-#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK     0x1
+#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK     0x1 /* bit2 */
 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT    2
-#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK     0x1
+#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK     0x1 /* bit3 */
 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT    3
-#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK     0x1
+#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK     0x1 /* bit4 */
 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT    4
-#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK     0x1
+#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK     0x1 /* bit5 */
 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT    5
-#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3 /* timer0cf */
 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     6
        u8 flags1;
-#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3 /* timer1cf */
 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     0
-#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3 /* timer2cf */
 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     2
-#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT     4
-#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3 /* cf4 */
 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT     6
        u8 flags2;
-#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3 /* cf5 */
 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT     0
-#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3 /* cf6 */
 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT     2
-#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK      0x3 /* cf7 */
 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT     4
-#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK      0x3 /* cf8 */
 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT     6
        u8 flags3;
-#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK      0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK      0x3 /* cf9 */
 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT     0
-#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK     0x3
+#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK     0x3 /* cf10 */
 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT    2
-#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   4
-#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   5
-#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   6
-#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   7
        u8 flags4;
-#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   0
-#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   1
-#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   2
-#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK    0x1 /* cf7en */
 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT   3
-#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK    0x1 /* cf8en */
 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT   4
-#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK    0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK    0x1 /* cf9en */
 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT   5
-#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK   0x1
+#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK   0x1 /* cf10en */
 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT  6
-#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
        u8 flags5;
-#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1 /* rule6en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1 /* rule7en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1
+#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1 /* rule8en */
 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
        __le32 reg0 /* reg0 */;
        __le32 reg1 /* reg1 */;
@@ -443,58 +536,58 @@ struct ustorm_core_conn_ag_ctx {
        u8 reserved /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
-#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1
+#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
-#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1
+#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
-#define USTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3 /* timer0cf */
 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
-#define USTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3 /* timer1cf */
 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
-#define USTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3 /* timer2cf */
 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
        u8 flags1;
-#define USTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT     0
-#define USTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3 /* cf4 */
 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT     2
-#define USTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3 /* cf5 */
 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT     4
-#define USTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3
+#define USTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3 /* cf6 */
 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT     6
        u8 flags2;
-#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
-#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
-#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
-#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   3
-#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   4
-#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   5
-#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1
+#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   6
-#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
        u8 flags3;
-#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1 /* rule6en */
 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1 /* rule7en */
 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1
+#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1 /* rule8en */
 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
        u8 byte2 /* byte2 */;
        u8 byte3 /* byte3 */;
@@ -526,27 +619,28 @@ struct ustorm_core_conn_st_ctx {
  * core connection context
  */
 struct core_conn_context {
-       struct ystorm_core_conn_st_ctx ystorm_st_context
-           /* ystorm storm context */;
+/* ystorm storm context */
+       struct ystorm_core_conn_st_ctx ystorm_st_context;
        struct regpair ystorm_st_padding[2] /* padding */;
-       struct pstorm_core_conn_st_ctx pstorm_st_context
-           /* pstorm storm context */;
+/* pstorm storm context */
+       struct pstorm_core_conn_st_ctx pstorm_st_context;
        struct regpair pstorm_st_padding[2] /* padding */;
-       struct xstorm_core_conn_st_ctx xstorm_st_context
-           /* xstorm storm context */;
-       struct xstorm_core_conn_ag_ctx xstorm_ag_context
-           /* xstorm aggregative context */;
-       struct tstorm_core_conn_ag_ctx tstorm_ag_context
-           /* tstorm aggregative context */;
-       struct ustorm_core_conn_ag_ctx ustorm_ag_context
-           /* ustorm aggregative context */;
-       struct mstorm_core_conn_st_ctx mstorm_st_context
-           /* mstorm storm context */;
-       struct ustorm_core_conn_st_ctx ustorm_st_context
-           /* ustorm storm context */;
+/* xstorm storm context */
+       struct xstorm_core_conn_st_ctx xstorm_st_context;
+/* xstorm aggregative context */
+       struct xstorm_core_conn_ag_ctx xstorm_ag_context;
+/* tstorm aggregative context */
+       struct tstorm_core_conn_ag_ctx tstorm_ag_context;
+/* ustorm aggregative context */
+       struct ustorm_core_conn_ag_ctx ustorm_ag_context;
+/* mstorm storm context */
+       struct mstorm_core_conn_st_ctx mstorm_st_context;
+/* ustorm storm context */
+       struct ustorm_core_conn_st_ctx ustorm_st_context;
        struct regpair ustorm_st_padding[2] /* padding */;
 };

+
 /*
  * How ll2 should deal with packet upon errors
  */
@@ -557,6 +651,7 @@ enum core_error_handle {
        MAX_CORE_ERROR_HANDLE
 };

+
 /*
  * opcodes for the event ring
  */
@@ -568,17 +663,19 @@ enum core_event_opcode {
        MAX_CORE_EVENT_OPCODE
 };

+
 /*
  * The L4 pseudo checksum mode for Core
  */
 enum core_l4_pseudo_checksum_mode {
-       CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH
-           ,
-       CORE_L4_PSEUDO_CSUM_ZERO_LENGTH
-           /* Pseudo Checksum on packet is calculated with zero length. */,
+/* Pseudo Checksum on packet is calculated with the correct packet length. */
+       CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
+/* Pseudo Checksum on packet is calculated with zero length. */
+       CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
        MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
 };

+
 /*
  * Light-L2 RX Producers in Tstorm RAM
  */
@@ -589,24 +686,26 @@ struct core_ll2_port_stats {
        struct regpair gsi_crcchksm_error;
 };

+
 /*
  * Ethernet TX Per Queue Stats
  */
 struct core_ll2_pstorm_per_queue_stat {
-       struct regpair sent_ucast_bytes
-           /* number of total bytes sent without errors */;
-       struct regpair sent_mcast_bytes
-           /* number of total bytes sent without errors */;
-       struct regpair sent_bcast_bytes
-           /* number of total bytes sent without errors */;
-       struct regpair sent_ucast_pkts
-           /* number of total packets sent without errors */;
-       struct regpair sent_mcast_pkts
-           /* number of total packets sent without errors */;
-       struct regpair sent_bcast_pkts
-           /* number of total packets sent without errors */;
+/* number of total bytes sent without errors */
+       struct regpair sent_ucast_bytes;
+/* number of total bytes sent without errors */
+       struct regpair sent_mcast_bytes;
+/* number of total bytes sent without errors */
+       struct regpair sent_bcast_bytes;
+/* number of total packets sent without errors */
+       struct regpair sent_ucast_pkts;
+/* number of total packets sent without errors */
+       struct regpair sent_mcast_pkts;
+/* number of total packets sent without errors */
+       struct regpair sent_bcast_pkts;
 };

+
 /*
  * Light-L2 RX Producers in Tstorm RAM
  */
@@ -616,13 +715,15 @@ struct core_ll2_rx_prod {
        __le32 reserved;
 };

+
 struct core_ll2_tstorm_per_queue_stat {
-       struct regpair packet_too_big_discard
-           /* Number of packets discarded because they are bigger than MTU */;
-       struct regpair no_buff_discard
-           /* Number of packets discarded due to lack of host buffers */;
+/* Number of packets discarded because they are bigger than MTU */
+       struct regpair packet_too_big_discard;
+/* Number of packets discarded due to lack of host buffers */
+       struct regpair no_buff_discard;
 };

+
 struct core_ll2_ustorm_per_queue_stat {
        struct regpair rcv_ucast_bytes;
        struct regpair rcv_mcast_bytes;
@@ -632,6 +733,7 @@ struct core_ll2_ustorm_per_queue_stat {
        struct regpair rcv_bcast_pkts;
 };

+
 /*
  * Core Ramrod Command IDs (light L2)
  */
@@ -644,6 +746,7 @@ enum core_ramrod_cmd_id {
        MAX_CORE_RAMROD_CMD_ID
 };

+
 /*
  * Core RX CQE Type for Light L2
  */
@@ -653,19 +756,23 @@ enum core_roce_flavor_type {
        MAX_CORE_ROCE_FLAVOR_TYPE
 };

+
 /*
  * Specifies how ll2 should deal with packets errors: packet_too_big and 
no_buff
  */
 struct core_rx_action_on_error {
        u8 error_type;
+/* ll2 how to handle error packet_too_big (use enum core_error_handle) */
 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK  0x3
 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
+/* ll2 how to handle error with no_buff  (use enum core_error_handle) */
 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK         0x3
 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT        2
 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK        0xF
 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT       4
 };

+
 /*
  * Core RX BD for Light L2
  */
@@ -674,6 +781,7 @@ struct core_rx_bd {
        __le16 reserved[4];
 };

+
 /*
  * Core RX CM offload BD for Light L2
  */
@@ -688,10 +796,12 @@ struct core_rx_bd_with_buff_len {
  */
 union core_rx_bd_union {
        struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */;
-       struct core_rx_bd_with_buff_len rx_bd_with_len
-           /* Core Rx Bd with dynamic buffer length */;
+/* Core Rx Bd with dynamic buffer length */
+       struct core_rx_bd_with_buff_len rx_bd_with_len;
 };

+
+
 /*
  * Opaque Data for Light L2 RX CQE .
  */
@@ -699,6 +809,7 @@ struct core_rx_cqe_opaque_data {
        __le32 data[2] /* Opaque CQE Data */;
 };

+
 /*
  * Core RX CQE Type for Light L2
  */
@@ -710,15 +821,16 @@ enum core_rx_cqe_type {
        MAX_CORE_RX_CQE_TYPE
 };

+
 /*
  * Core RX CQE for Light L2 .
  */
 struct core_rx_fast_path_cqe {
        u8 type /* CQE type */;
-       u8 placement_offset
-           /* Offset (in bytes) of the packet from start of the buffer */;
-       struct parsing_and_err_flags parse_flags
-           /* Parsing and error flags from the parser */;
+/* Offset (in bytes) of the packet from start of the buffer */
+       u8 placement_offset;
+/* Parsing and error flags from the parser */
+       struct parsing_and_err_flags parse_flags;
        __le16 packet_length /* Total packet length (from the parser) */;
        __le16 vlan /* 802.1q VLAN tag */;
        struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
@@ -731,8 +843,8 @@ struct core_rx_fast_path_cqe {
 struct core_rx_gsi_offload_cqe {
        u8 type /* CQE type */;
        u8 data_length_error /* set if gsi data is bigger than buff */;
-       struct parsing_and_err_flags parse_flags
-           /* Parsing and error flags from the parser */;
+/* Parsing and error flags from the parser */
+       struct parsing_and_err_flags parse_flags;
        __le16 data_length /* Total packet length (from the parser) */;
        __le16 vlan /* 802.1q VLAN tag */;
        __le32 src_mac_addrhi /* hi 4 bytes source mac address */;
@@ -760,6 +872,10 @@ union core_rx_cqe_union {
        struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */;
 };

+
+
+
+
 /*
  * Ramrod data for rx queue start ramrod
  */
@@ -773,18 +889,28 @@ struct core_rx_start_ramrod_data {
        u8 complete_event_flg /* post completion to the event ring if set */;
        u8 drop_ttl0_flg /* drop packet with ttl0 if set */;
        __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
-       u8 inner_vlan_removal_en
-           /* if set, 802.1q tags will be removed and copied to CQE */;
+/* if set, 802.1q tags will be removed and copied to CQE */
+       u8 inner_vlan_removal_en;
        u8 queue_id /* Light L2 RX Queue ID */;
        u8 main_func_queue /* Is this the main queue for the PF */;
+/* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if
+ * main_func_queue is set.
+ */
        u8 mf_si_bcast_accept_all;
+/* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if
+ * main_func_queue is set.
+ */
        u8 mf_si_mcast_accept_all;
+/* Specifies how ll2 should deal with packets errors: packet_too_big and
+ * no_buff
+ */
        struct core_rx_action_on_error action_on_error;
-       u8 gsi_offload_flag
-           /* set when in GSI offload mode on ROCE connection */;
+/* set when in GSI offload mode on ROCE connection */
+       u8 gsi_offload_flag;
        u8 reserved[7];
 };

+
 /*
  * Ramrod data for rx queue stop ramrod
  */
@@ -796,25 +922,38 @@ struct core_rx_stop_ramrod_data {
        __le16 reserved2[2];
 };

+
 /*
  * Flags for Core TX BD
  */
 struct core_tx_bd_flags {
        u8 as_bitfield;
+/* Do not allow additional VLAN manipulations on this packet (DCB) */
 #define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_MASK      0x1
 #define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_SHIFT     0
+/* Insert VLAN into packet */
 #define CORE_TX_BD_FLAGS_VLAN_INSERTION_MASK       0x1
 #define CORE_TX_BD_FLAGS_VLAN_INSERTION_SHIFT      1
+/* This is the first BD of the packet (for debug) */
 #define CORE_TX_BD_FLAGS_START_BD_MASK             0x1
 #define CORE_TX_BD_FLAGS_START_BD_SHIFT            2
+/* Calculate the IP checksum for the packet */
 #define CORE_TX_BD_FLAGS_IP_CSUM_MASK              0x1
 #define CORE_TX_BD_FLAGS_IP_CSUM_SHIFT             3
+/* Calculate the L4 checksum for the packet */
 #define CORE_TX_BD_FLAGS_L4_CSUM_MASK              0x1
 #define CORE_TX_BD_FLAGS_L4_CSUM_SHIFT             4
+/* Packet is IPv6 with extensions */
 #define CORE_TX_BD_FLAGS_IPV6_EXT_MASK             0x1
 #define CORE_TX_BD_FLAGS_IPV6_EXT_SHIFT            5
+/* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol:
+ * 0-TCP, 1-UDP
+ */
 #define CORE_TX_BD_FLAGS_L4_PROTOCOL_MASK          0x1
 #define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT         6
+/* The pseudo checksum mode to place in the L4 checksum field. Required only
+ *  when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode)
+ */
 #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK  0x1
 #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7
 };
@@ -853,6 +992,8 @@ struct core_tx_bd {
 #define CORE_TX_BD_RESERVED1_SHIFT       15
 };

+
+
 /*
  * Light L2 TX Destination
  */
@@ -862,6 +1003,7 @@ enum core_tx_dest {
        MAX_CORE_TX_DEST
 };

+
 /*
  * Ramrod data for tx queue start ramrod
  */
@@ -875,11 +1017,12 @@ struct core_tx_start_ramrod_data {
        u8 conn_type /* connection type that loaded ll2 */;
        __le16 pbl_size /* Number of BD pages pointed by PBL */;
        __le16 qm_pq_id /* QM PQ ID */;
-       u8 gsi_offload_flag
-           /* set when in GSI offload mode on ROCE connection */;
+/* set when in GSI offload mode on ROCE connection */
+       u8 gsi_offload_flag;
        u8 resrved[3];
 };

+
 /*
  * Ramrod data for tx queue stop ramrod
  */
@@ -887,6 +1030,7 @@ struct core_tx_stop_ramrod_data {
        __le32 reserved0[2];
 };

+
 /*
  * Enum flag for what type of dcb data to update
  */
@@ -899,6 +1043,7 @@ enum dcb_dhcp_update_flag {
        MAX_DCB_DHCP_UPDATE_FLAG
 };

+
 struct eth_mstorm_per_pf_stat {
        struct regpair gre_discard_pkts /* Dropped GRE RX packets */;
        struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */;
@@ -906,17 +1051,27 @@ struct eth_mstorm_per_pf_stat {
        struct regpair lb_discard_pkts /* Dropped Tx switched packets */;
 };

+
 struct eth_mstorm_per_queue_stat {
+/* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (IPv6) */
        struct regpair ttl0_discard;
+/* Number of packets discarded because they are bigger than MTU */
        struct regpair packet_too_big_discard;
+/* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */
        struct regpair no_buff_discard;
+/* Number of packets discarded because of no active Rx connection */
        struct regpair not_active_discard;
+/* number of coalesced packets in all TPA aggregations */
        struct regpair tpa_coalesced_pkts;
+/* total number of TPA aggregations */
        struct regpair tpa_coalesced_events;
+/* number of aggregations, which abnormally ended */
        struct regpair tpa_aborts_num;
+/* total TCP payload length in all TPA aggregations */
        struct regpair tpa_coalesced_bytes;
 };

+
 /*
  * Ethernet TX Per PF
  */
@@ -944,38 +1099,42 @@ struct eth_pstorm_per_pf_stat {
        struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */;
 };

+
 /*
  * Ethernet TX Per Queue Stats
  */
 struct eth_pstorm_per_queue_stat {
-       struct regpair sent_ucast_bytes
-           /* number of total bytes sent without errors */;
-       struct regpair sent_mcast_bytes
-           /* number of total bytes sent without errors */;
-       struct regpair sent_bcast_bytes
-           /* number of total bytes sent without errors */;
-       struct regpair sent_ucast_pkts
-           /* number of total packets sent without errors */;
-       struct regpair sent_mcast_pkts
-           /* number of total packets sent without errors */;
-       struct regpair sent_bcast_pkts
-           /* number of total packets sent without errors */;
-       struct regpair error_drop_pkts
-           /* number of total packets dropped due to errors */;
+/* number of total bytes sent without errors */
+       struct regpair sent_ucast_bytes;
+/* number of total bytes sent without errors */
+       struct regpair sent_mcast_bytes;
+/* number of total bytes sent without errors */
+       struct regpair sent_bcast_bytes;
+/* number of total packets sent without errors */
+       struct regpair sent_ucast_pkts;
+/* number of total packets sent without errors */
+       struct regpair sent_mcast_pkts;
+/* number of total packets sent without errors */
+       struct regpair sent_bcast_pkts;
+/* number of total packets dropped due to errors */
+       struct regpair error_drop_pkts;
 };

+
 /*
  * ETH Rx producers data
  */
 struct eth_rx_rate_limit {
+/* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) 
*/
        __le16 mult;
-       __le16 cnst
-           /* Constant term to add (or subtract from number of cycles) */;
+/* Constant term to add (or subtract from number of cycles) */
+       __le16 cnst;
        u8 add_sub_cnst /* Add (1) or subtract (0) constant term */;
        u8 reserved0;
        __le16 reserved1;
 };

+
 struct eth_ustorm_per_pf_stat {
 /* number of total ucast bytes received on loopback port without errors */
        struct regpair rcv_lb_ucast_bytes;
@@ -997,6 +1156,7 @@ struct eth_ustorm_per_pf_stat {
        struct regpair rcv_geneve_pkts /* Received GENEVE packets */;
 };

+
 struct eth_ustorm_per_queue_stat {
        struct regpair rcv_ucast_bytes;
        struct regpair rcv_mcast_bytes;
@@ -1006,6 +1166,7 @@ struct eth_ustorm_per_queue_stat {
        struct regpair rcv_bcast_pkts;
 };

+
 /*
  * Event Ring Next Page Address
  */
@@ -1019,10 +1180,12 @@ struct event_ring_next_addr {
  */
 union event_ring_element {
        struct event_ring_entry entry /* Event Ring Entry */;
-       struct event_ring_next_addr next_addr /* Event Ring Next Page Address */
-         ;
+/* Event Ring Next Page Address */
+       struct event_ring_next_addr next_addr;
 };

+
+
 /*
  * Ports mode
  */
@@ -1032,6 +1195,7 @@ enum fw_flow_ctrl_mode {
        MAX_FW_FLOW_CTRL_MODE
 };

+
 /*
  * Major and Minor hsi Versions
  */
@@ -1040,6 +1204,7 @@ struct hsi_fp_ver_struct {
        u8 major_ver_arr[2] /* Major Version of driver loading pf */;
 };

+
 /*
  * Integration Phase
  */
@@ -1050,6 +1215,7 @@ enum integ_phase {
        MAX_INTEG_PHASE
 };

+
 /*
  * Ports mode
  */
@@ -1062,61 +1228,69 @@ enum iwarp_ll2_tx_queues {
        MAX_IWARP_LL2_TX_QUEUES
 };

+
 /*
  * Malicious VF error ID
  */
 enum malicious_vf_error_id {
        MALICIOUS_VF_NO_ERROR /* Zero placeholder value */,
-       VF_PF_CHANNEL_NOT_READY
-           /* Writing to VF/PF channel when it is not ready */,
+/* Writing to VF/PF channel when it is not ready */
+       VF_PF_CHANNEL_NOT_READY,
        VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,
        VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,
-       ETH_PACKET_TOO_SMALL
-           /* TX packet is shorter then reported on BDs or from minimal size */
-           ,
-       ETH_ILLEGAL_VLAN_MODE
-           /* Tx packet with marked as insert VLAN when its illegal */,
+/* TX packet is shorter then reported on BDs or from minimal size */
+       ETH_PACKET_TOO_SMALL,
+/* Tx packet with marked as insert VLAN when its illegal */
+       ETH_ILLEGAL_VLAN_MODE,
        ETH_MTU_VIOLATION /* TX packet is greater then MTU */,
-       ETH_ILLEGAL_INBAND_TAGS /* TX packet has illegal inband tags marked */,
-       ETH_VLAN_INSERT_AND_INBAND_VLAN /* Vlan cant be added to inband tag */,
-       ETH_ILLEGAL_NBDS /* indicated number of BDs for the packet is illegal */
-           ,
+/* TX packet has illegal inband tags marked */
+       ETH_ILLEGAL_INBAND_TAGS,
+/* Vlan cant be added to inband tag */
+       ETH_VLAN_INSERT_AND_INBAND_VLAN,
+/* indicated number of BDs for the packet is illegal */
+       ETH_ILLEGAL_NBDS,
        ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */,
-       ETH_INSUFFICIENT_BDS
-           /* There are not enough BDs for transmission of even one packet */,
+/* There are not enough BDs for transmission of even one packet */
+       ETH_INSUFFICIENT_BDS,
        ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */,
        ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */,
-       ETH_ZERO_SIZE_BD
-           /* empty BD (which not contains control flags) is illegal  */,
+/* empty BD (which not contains control flags) is illegal  */
+       ETH_ZERO_SIZE_BD,
        ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit  */,
-       ETH_INSUFFICIENT_PAYLOAD
-           ,
+/* In LSO its expected that on the local BD ring there will be at least MSS
+ * bytes of data
+ */
+       ETH_INSUFFICIENT_PAYLOAD,
        ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */,
-       ETH_TUNN_IPV6_EXT_NBD_ERR
-           /* Tunneled packet with IPv6+Ext without a proper number of BDs */,
+/* Tunneled packet with IPv6+Ext without a proper number of BDs */
+       ETH_TUNN_IPV6_EXT_NBD_ERR,
        ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
        MAX_MALICIOUS_VF_ERROR_ID
 };

+
+
 /*
  * Mstorm non-triggering VF zone
  */
 struct mstorm_non_trigger_vf_zone {
-       struct eth_mstorm_per_queue_stat eth_queue_stat
-           /* VF statistic bucket */;
+/* VF statistic bucket */
+       struct eth_mstorm_per_queue_stat eth_queue_stat;
 /* VF RX queues producers */
        struct eth_rx_prod_data
                eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
 };

+
 /*
  * Mstorm VF zone
  */
 struct mstorm_vf_zone {
-       struct mstorm_non_trigger_vf_zone non_trigger
-           /* non-interrupt-triggering zone */;
+/* non-interrupt-triggering zone */
+       struct mstorm_non_trigger_vf_zone non_trigger;
 };

+
 /*
  * personality per PF
  */
@@ -1132,25 +1306,27 @@ enum personality_type {
        MAX_PERSONALITY_TYPE
 };

+
 /*
  * tunnel configuration
  */
 struct pf_start_tunnel_config {
-       u8 set_vxlan_udp_port_flg /* Set VXLAN tunnel UDP destination port. */;
-       u8 set_geneve_udp_port_flg /* Set GENEVE tunnel UDP destination port. */
-         ;
+/* Set VXLAN tunnel UDP destination port. */
+       u8 set_vxlan_udp_port_flg;
+/* Set GENEVE tunnel UDP destination port. */
+       u8 set_geneve_udp_port_flg;
        u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
-       u8 tx_enable_l2geneve /* If set, enable l2 GENEVE tunnel in TX path. */
-         ;
-       u8 tx_enable_ipgeneve /* If set, enable IP GENEVE tunnel in TX path. */
-         ;
+/* If set, enable l2 GENEVE tunnel in TX path. */
+       u8 tx_enable_l2geneve;
+/* If set, enable IP GENEVE tunnel in TX path. */
+       u8 tx_enable_ipgeneve;
        u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
        u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
        u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
-       u8 tunnel_clss_l2geneve
-           /* Classification scheme for l2 GENEVE tunnel. */;
-       u8 tunnel_clss_ipgeneve
-           /* Classification scheme for ip GENEVE tunnel. */;
+/* Classification scheme for l2 GENEVE tunnel. */
+       u8 tunnel_clss_l2geneve;
+/* Classification scheme for ip GENEVE tunnel. */
+       u8 tunnel_clss_ipgeneve;
        u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;
        u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
        __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
@@ -1162,34 +1338,43 @@ struct pf_start_tunnel_config {
  */
 struct pf_start_ramrod_data {
        struct regpair event_ring_pbl_addr /* Address of event ring PBL */;
-       struct regpair consolid_q_pbl_addr
-           /* PBL address of consolidation queue */;
-       struct pf_start_tunnel_config tunnel_config /* tunnel configuration. */
-         ;
+/* PBL address of consolidation queue */
+       struct regpair consolid_q_pbl_addr;
+/* tunnel configuration. */
+       struct pf_start_tunnel_config tunnel_config;
        __le16 event_ring_sb_id /* Status block ID */;
+/* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */
        u8 base_vf_id;
-         ;
        u8 num_vfs /* Amount of vfs owned by PF */;
        u8 event_ring_num_pages /* Number of PBL pages in event ring */;
        u8 event_ring_sb_index /* Status block index */;
        u8 path_id /* HW path ID (engine ID) */;
        u8 warning_as_error /* In FW asserts, treat warning as error */;
-       u8 dont_log_ramrods
-           /* If not set - throw a warning for each ramrod (for debug) */;
+/* If not set - throw a warning for each ramrod (for debug) */
+       u8 dont_log_ramrods;
        u8 personality /* define what type of personality is new PF */;
+/* Log type mask. Each bit set enables a corresponding event type logging.
+ * Event types are defined as ASSERT_LOG_TYPE_xxx
+ */
        __le16 log_type_mask;
        u8 mf_mode /* Multi function mode */;
        u8 integ_phase /* Integration phase */;
+/* If set, inter-pf tx switching is allowed in Switch Independent func mode */
        u8 allow_npar_tx_switching;
+/* Map from inner to outer priority. Set pri_map_valid when init map */
        u8 inner_to_outer_pri_map[8];
-       u8 pri_map_valid
-           /* If inner_to_outer_pri_map is initialize then set pri_map_valid */
-         ;
+/* If inner_to_outer_pri_map is initialize then set pri_map_valid */
+       u8 pri_map_valid;
+/* In case mf_mode is MF_OVLAN, this field specifies the outer vlan
+ * (lower 16 bits) and ethType to use (higher 16 bits)
+ */
        __le32 outer_tag;
 /* FP HSI version to be used by FW */
        struct hsi_fp_ver_struct hsi_fp_ver;
 };

+
+
 /*
  * Data for port update ramrod
  */
@@ -1203,9 +1388,10 @@ struct protocol_dcb_data {
 };

 /*
- * tunnel configuration
+ * Update tunnel configuration
  */
 struct pf_update_tunnel_config {
+/* Update RX per PF tunnel classification scheme. */
        u8 update_rx_pf_clss;
 /* Update per PORT default tunnel RX classification scheme for traffic with
  * unknown unicast outer MAC in NPAR mode.
@@ -1215,23 +1401,24 @@ struct pf_update_tunnel_config {
  * unicast outer MAC in NPAR mode.
  */
        u8 update_rx_def_non_ucast_clss;
+/* Update TX per PF tunnel classification scheme. used by pf update. */
        u8 update_tx_pf_clss;
-       u8 set_vxlan_udp_port_flg
-           /* Update VXLAN tunnel UDP destination port. */;
-       u8 set_geneve_udp_port_flg
-           /* Update GENEVE tunnel UDP destination port. */;
+/* Update VXLAN tunnel UDP destination port. */
+       u8 set_vxlan_udp_port_flg;
+/* Update GENEVE tunnel UDP destination port. */
+       u8 set_geneve_udp_port_flg;
        u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
-       u8 tx_enable_l2geneve /* If set, enable l2 GENEVE tunnel in TX path. */
-         ;
-       u8 tx_enable_ipgeneve /* If set, enable IP GENEVE tunnel in TX path. */
-         ;
+/* If set, enable l2 GENEVE tunnel in TX path. */
+       u8 tx_enable_l2geneve;
+/* If set, enable IP GENEVE tunnel in TX path. */
+       u8 tx_enable_ipgeneve;
        u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
        u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
        u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
-       u8 tunnel_clss_l2geneve
-           /* Classification scheme for l2 GENEVE tunnel. */;
-       u8 tunnel_clss_ipgeneve
-           /* Classification scheme for ip GENEVE tunnel. */;
+/* Classification scheme for l2 GENEVE tunnel. */
+       u8 tunnel_clss_l2geneve;
+/* Classification scheme for ip GENEVE tunnel. */
+       u8 tunnel_clss_ipgeneve;
        u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;
        u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
        __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
@@ -1254,19 +1441,21 @@ struct pf_update_ramrod_data {
        u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
        struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
        struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
-       struct protocol_dcb_data iscsi_dcb_data /* core iscsi related fields */
-         ;
+/* core iscsi related fields */
+       struct protocol_dcb_data iscsi_dcb_data;
        struct protocol_dcb_data roce_dcb_data /* core roce related fields */;
-       struct protocol_dcb_data iwarp_dcb_data /* core iwarp related fields */
-         ;
 /* core roce related fields */
        struct protocol_dcb_data rroce_dcb_data;
+/* core iwarp related fields */
+       struct protocol_dcb_data iwarp_dcb_data;
        __le16 mf_vlan /* new outer vlan id value */;
        __le16 reserved;
 /* tunnel configuration. */
        struct pf_update_tunnel_config tunnel_config;
 };

+
+
 /*
  * Ports mode
  */
@@ -1279,6 +1468,8 @@ enum ports_mode {
        MAX_PORTS_MODE
 };

+
+
 /*
  * use to index in hsi_fp_[major|minor]_ver_arr per protocol
  */
@@ -1288,6 +1479,8 @@ enum protocol_version_array_key {
        MAX_PROTOCOL_VERSION_ARRAY_KEY
 };

+
+
 /*
  * RDMA TX Stats
  */
@@ -1300,20 +1493,22 @@ struct rdma_sent_stats {
  * Pstorm non-triggering VF zone
  */
 struct pstorm_non_trigger_vf_zone {
-       struct eth_pstorm_per_queue_stat eth_queue_stat
-           /* VF statistic bucket */;
+/* VF statistic bucket */
+       struct eth_pstorm_per_queue_stat eth_queue_stat;
        struct rdma_sent_stats rdma_stats /* RoCE sent statistics */;
 };

+
 /*
  * Pstorm VF zone
  */
 struct pstorm_vf_zone {
-       struct pstorm_non_trigger_vf_zone non_trigger
-           /* non-interrupt-triggering zone */;
+/* non-interrupt-triggering zone */
+       struct pstorm_non_trigger_vf_zone non_trigger;
        struct regpair reserved[7] /* vf_zone size mus be power of 2 */;
 };

+
 /*
  * Ramrod Header of SPQE
  */
@@ -1324,6 +1519,7 @@ struct ramrod_header {
        __le16 echo /* Ramrod echo */;
 };

+
 /*
  * RDMA RX Stats
  */
@@ -1332,6 +1528,8 @@ struct rdma_rcv_stats {
        struct regpair rcv_pkts /* number of total RDMA packets received */;
 };

+
+
 /*
  * Data for update QCN/DCQCN RL ramrod
  */
@@ -1357,6 +1555,7 @@ struct rl_update_ramrod_data {
        __le32 reserved[2];
 };

+
 /*
  * Slowpath Element (SPQE)
  */
@@ -1365,6 +1564,7 @@ struct slow_path_element {
        struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */;
 };

+
 /*
  * Tstorm non-triggering VF zone
  */
@@ -1372,28 +1572,36 @@ struct tstorm_non_trigger_vf_zone {
        struct rdma_rcv_stats rdma_stats /* RoCE received statistics */;
 };

+
 struct tstorm_per_port_stat {
-       struct regpair trunc_error_discard
-           /* packet is dropped because it was truncated in NIG */;
-       struct regpair mac_error_discard
-           /* packet is dropped because of Ethernet FCS error */;
-       struct regpair mftag_filter_discard
-           /* packet is dropped because classification was unsuccessful */;
+/* packet is dropped because it was truncated in NIG */
+       struct regpair trunc_error_discard;
+/* packet is dropped because of Ethernet FCS error */
+       struct regpair mac_error_discard;
+/* packet is dropped because classification was unsuccessful */
+       struct regpair mftag_filter_discard;
+/* packet was passed to Ethernet and dropped because of no mac filter match */
        struct regpair eth_mac_filter_discard;
+/* packet passed to Light L2 and dropped because Light L2 is not configured for
+ * this PF
+ */
        struct regpair ll2_mac_filter_discard;
+/* packet passed to Light L2 and dropped because Light L2 is not configured for
+ * this PF
+ */
        struct regpair ll2_conn_disabled_discard;
-       struct regpair iscsi_irregular_pkt
-           /* packet is an ISCSI irregular packet */;
-       struct regpair fcoe_irregular_pkt
-           /* packet is an FCOE irregular packet */;
-       struct regpair roce_irregular_pkt
-           /* packet is an ROCE irregular packet */;
-       struct regpair eth_irregular_pkt /* packet is an ETH irregular packet */
-         ;
-       struct regpair toe_irregular_pkt /* packet is an TOE irregular packet */
-         ;
-       struct regpair preroce_irregular_pkt
-           /* packet is an PREROCE irregular packet */;
+/* packet is an ISCSI irregular packet */
+       struct regpair iscsi_irregular_pkt;
+/* packet is an FCOE irregular packet */
+       struct regpair fcoe_irregular_pkt;
+/* packet is an ROCE irregular packet */
+       struct regpair roce_irregular_pkt;
+/* packet is an ETH irregular packet */
+       struct regpair eth_irregular_pkt;
+/* packet is an TOE irregular packet */
+       struct regpair toe_irregular_pkt;
+/* packet is an PREROCE irregular packet */
+       struct regpair preroce_irregular_pkt;
        struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */;
 /* VXLAN dropped packets */
        struct regpair eth_vxlan_tunn_filter_discard;
@@ -1401,29 +1609,32 @@ struct tstorm_per_port_stat {
        struct regpair eth_geneve_tunn_filter_discard;
 };

+
 /*
  * Tstorm VF zone
  */
 struct tstorm_vf_zone {
-       struct tstorm_non_trigger_vf_zone non_trigger
-           /* non-interrupt-triggering zone */;
+/* non-interrupt-triggering zone */
+       struct tstorm_non_trigger_vf_zone non_trigger;
 };

+
 /*
  * Tunnel classification scheme
  */
 enum tunnel_clss {
-       TUNNEL_CLSS_MAC_VLAN =
-           0
-           /* Use MAC & VLAN from first L2 header for vport classification. */
-           ,
-       TUNNEL_CLSS_MAC_VNI
-           ,
-       TUNNEL_CLSS_INNER_MAC_VLAN
-           /* Use MAC and VLAN from last L2 header for vport classification */
-           ,
-       TUNNEL_CLSS_INNER_MAC_VNI
-           ,
+/* Use MAC and VLAN from first L2 header for vport classification. */
+       TUNNEL_CLSS_MAC_VLAN = 0,
+/* Use MAC from first L2 header and VNI from tunnel header for vport
+ * classification
+ */
+       TUNNEL_CLSS_MAC_VNI,
+/* Use MAC and VLAN from last L2 header for vport classification */
+       TUNNEL_CLSS_INNER_MAC_VLAN,
+/* Use MAC from last L2 header and VNI from tunnel header for vport
+ * classification
+ */
+       TUNNEL_CLSS_INNER_MAC_VNI,
 /* Use MAC and VLAN from last L2 header for vport classification. If no exact
  * match, use MAC and VLAN from first L2 header for classification.
  */
@@ -1431,15 +1642,18 @@ enum tunnel_clss {
        MAX_TUNNEL_CLSS
 };

+
+
 /*
  * Ustorm non-triggering VF zone
  */
 struct ustorm_non_trigger_vf_zone {
-       struct eth_ustorm_per_queue_stat eth_queue_stat
-           /* VF statistic bucket */;
+/* VF statistic bucket */
+       struct eth_ustorm_per_queue_stat eth_queue_stat;
        struct regpair vf_pf_msg_addr /* VF-PF message address */;
 };

+
 /*
  * Ustorm triggering VF zone
  */
@@ -1448,30 +1662,40 @@ struct ustorm_trigger_vf_zone {
        u8 reserved[7];
 };

+
 /*
  * Ustorm VF zone
  */
 struct ustorm_vf_zone {
-       struct ustorm_non_trigger_vf_zone non_trigger
-           /* non-interrupt-triggering zone */;
+/* non-interrupt-triggering zone */
+       struct ustorm_non_trigger_vf_zone non_trigger;
        struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */;
 };

+
 /*
  * VF-PF channel data
  */
 struct vf_pf_channel_data {
+/* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel
+ * is ready for a new transaction.
+ */
        __le32 ready;
+/* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is
+ * valid.
+ */
        u8 valid;
        u8 reserved0;
        __le16 reserved1;
 };

+
 /*
  * Ramrod data for VF start ramrod
  */
 struct vf_start_ramrod_data {
        u8 vf_id /* VF ID */;
+/* If set, initial cleanup ack will be sent to parent PF SP event queue */
        u8 enable_flr_ack;
        __le16 opaque_fid /* VF opaque FID */;
        u8 personality /* define what type of personality is new VF */;
@@ -1480,6 +1704,7 @@ struct vf_start_ramrod_data {
        struct hsi_fp_ver_struct hsi_fp_ver;
 };

+
 /*
  * Ramrod data for VF start ramrod
  */
@@ -1490,6 +1715,7 @@ struct vf_stop_ramrod_data {
        __le32 reserved2;
 };

+
 /*
  * VF zone size mode.
  */
@@ -1503,6 +1729,9 @@ enum vf_zone_size_mode {
        MAX_VF_ZONE_SIZE_MODE
 };

+
+
+
 /*
  * Attentions status block
  */
@@ -1517,6 +1746,7 @@ struct atten_status_block {

 /*
  * Igu cleanup bit values to distinguish between clean or producer consumer
+ * update.
  */
 enum command_type_bit {
        IGU_COMMAND_TYPE_NOP = 0,
@@ -1524,61 +1754,100 @@ enum command_type_bit {
        MAX_COMMAND_TYPE_BIT
 };

+
 /*
  * DMAE command
  */
 struct dmae_cmd {
        __le32 opcode;
+/* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */
 #define DMAE_CMD_SRC_MASK              0x1
 #define DMAE_CMD_SRC_SHIFT             0
+/* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None
+ * (use enum dmae_cmd_dst_enum)
+ */
 #define DMAE_CMD_DST_MASK              0x3
 #define DMAE_CMD_DST_SHIFT             1
+/* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */
 #define DMAE_CMD_C_DST_MASK            0x1
 #define DMAE_CMD_C_DST_SHIFT           3
+/* Reset the CRC result (do not use the previous result as the seed) */
 #define DMAE_CMD_CRC_RESET_MASK        0x1
 #define DMAE_CMD_CRC_RESET_SHIFT       4
+/* Reset the source address in the next go to the same source address of the
+ * previous go
+ */
 #define DMAE_CMD_SRC_ADDR_RESET_MASK   0x1
 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT  5
+/* Reset the destination address in the next go to the same destination address
+ * of the previous go
+ */
 #define DMAE_CMD_DST_ADDR_RESET_MASK   0x1
 #define DMAE_CMD_DST_ADDR_RESET_SHIFT  6
+/* 0   completion function is the same as src function, 1 - 0 completion
+ * function is the same as dst function (use enum dmae_cmd_comp_func_enum)
+ */
 #define DMAE_CMD_COMP_FUNC_MASK        0x1
 #define DMAE_CMD_COMP_FUNC_SHIFT       7
+/* 0 - Do not write a completion word, 1 - Write a completion word
+ * (use enum dmae_cmd_comp_word_en_enum)
+ */
 #define DMAE_CMD_COMP_WORD_EN_MASK     0x1
 #define DMAE_CMD_COMP_WORD_EN_SHIFT    8
+/* 0 - Do not write a CRC word, 1 - Write a CRC word
+ * (use enum dmae_cmd_comp_crc_en_enum)
+ */
 #define DMAE_CMD_COMP_CRC_EN_MASK      0x1
 #define DMAE_CMD_COMP_CRC_EN_SHIFT     9
+/* The CRC word should be taken from the DMAE address space from address 9+X,
+ * where X is the value in these bits.
+ */
 #define DMAE_CMD_COMP_CRC_OFFSET_MASK  0x7
 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
 #define DMAE_CMD_RESERVED1_MASK        0x1
 #define DMAE_CMD_RESERVED1_SHIFT       13
 #define DMAE_CMD_ENDIANITY_MODE_MASK   0x3
 #define DMAE_CMD_ENDIANITY_MODE_SHIFT  14
+/* The field specifies how the completion word is affected by PCIe read error. 0
+ * Send a regular completion, 1 - Send a completion with an error indication,
+ * 2 do not send a completion (use enum dmae_cmd_error_handling_enum)
+ */
 #define DMAE_CMD_ERR_HANDLING_MASK     0x3
 #define DMAE_CMD_ERR_HANDLING_SHIFT    16
+/* The port ID to be placed on the  RF FID  field of the GRC bus. this field is
+ * used both when GRC is the destination and when it is the source of the DMAE
+ * transaction.
+ */
 #define DMAE_CMD_PORT_ID_MASK          0x3
 #define DMAE_CMD_PORT_ID_SHIFT         18
+/* Source PCI function number [3:0] */
 #define DMAE_CMD_SRC_PF_ID_MASK        0xF
 #define DMAE_CMD_SRC_PF_ID_SHIFT       20
+/* Destination PCI function number [3:0] */
 #define DMAE_CMD_DST_PF_ID_MASK        0xF
 #define DMAE_CMD_DST_PF_ID_SHIFT       24
-#define DMAE_CMD_SRC_VF_ID_VALID_MASK  0x1
+#define DMAE_CMD_SRC_VF_ID_VALID_MASK  0x1 /* Source VFID valid */
 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
-#define DMAE_CMD_DST_VF_ID_VALID_MASK  0x1
+#define DMAE_CMD_DST_VF_ID_VALID_MASK  0x1 /* Destination VFID valid */
 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
 #define DMAE_CMD_RESERVED2_MASK        0x3
 #define DMAE_CMD_RESERVED2_SHIFT       30
-       __le32 src_addr_lo
-           /* PCIe source address low in bytes or GRC source address in DW */;
+/* PCIe source address low in bytes or GRC source address in DW */
+       __le32 src_addr_lo;
+/* PCIe source address high in bytes or reserved (if source is GRC) */
        __le32 src_addr_hi;
+/* PCIe destination address low in bytes or GRC destination address in DW */
        __le32 dst_addr_lo;
+/* PCIe destination address high in bytes or reserved (if destination is GRC) 
*/
        __le32 dst_addr_hi;
        __le16 length_dw /* Length in DW */;
        __le16 opcode_b;
-#define DMAE_CMD_SRC_VF_ID_MASK        0xFF
+#define DMAE_CMD_SRC_VF_ID_MASK        0xFF /* Source VF id */
 #define DMAE_CMD_SRC_VF_ID_SHIFT       0
-#define DMAE_CMD_DST_VF_ID_MASK        0xFF
+#define DMAE_CMD_DST_VF_ID_MASK        0xFF /* Destination VF id */
 #define DMAE_CMD_DST_VF_ID_SHIFT       8
        __le32 comp_addr_lo /* PCIe completion address low or grc address */;
+/* PCIe completion address high or reserved (if completion address is in GRC) 
*/
        __le32 comp_addr_hi;
        __le32 comp_val /* Value to write to completion address */;
        __le32 crc32 /* crc16 result */;
@@ -1649,6 +1918,7 @@ enum dmae_cmd_src_enum {
        MAX_DMAE_CMD_SRC_ENUM
 };

+
 /*
  * IGU cleanup command
  */
@@ -1656,15 +1926,18 @@ struct igu_cleanup {
        __le32 sb_id_and_flags;
 #define IGU_CLEANUP_RESERVED0_MASK     0x7FFFFFF
 #define IGU_CLEANUP_RESERVED0_SHIFT    0
+/* cleanup clear - 0, set - 1 */
 #define IGU_CLEANUP_CLEANUP_SET_MASK   0x1
 #define IGU_CLEANUP_CLEANUP_SET_SHIFT  27
 #define IGU_CLEANUP_CLEANUP_TYPE_MASK  0x7
 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
+/* must always be set (use enum command_type_bit) */
 #define IGU_CLEANUP_COMMAND_TYPE_MASK  0x1
 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
        __le32 reserved1;
 };

+
 /*
  * IGU firmware driver command
  */
@@ -1673,6 +1946,7 @@ union igu_command {
        struct igu_cleanup cleanup;
 };

+
 /*
  * IGU firmware driver command
  */
@@ -1683,10 +1957,12 @@ struct igu_command_reg_ctrl {
 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
+/* command typ: 0 - read, 1 - write */
 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
 };

+
 /*
  * IGU mapping line structure
  */
@@ -1696,9 +1972,10 @@ struct igu_mapping_line {
 #define IGU_MAPPING_LINE_VALID_SHIFT           0
 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK    0xFF
 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT   1
+/* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */
 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK  0xFF
 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
-#define IGU_MAPPING_LINE_PF_VALID_MASK         0x1
+#define IGU_MAPPING_LINE_PF_VALID_MASK         0x1 /* PF-1, VF-0 */
 #define IGU_MAPPING_LINE_PF_VALID_SHIFT        17
 #define IGU_MAPPING_LINE_IPS_GROUP_MASK        0x3F
 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT       18
@@ -1706,6 +1983,7 @@ struct igu_mapping_line {
 #define IGU_MAPPING_LINE_RESERVED_SHIFT        24
 };

+
 /*
  * IGU MSIX line structure
  */
@@ -1728,32 +2006,32 @@ struct mstorm_core_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
-#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1
+#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
-#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1
+#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
-#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3
+#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
-#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3
+#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
-#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3
+#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
        u8 flags1;
-#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1
+#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
-#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1
+#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
-#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1
+#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
-#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1
+#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1
+#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1
+#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1
+#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1
+#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
        __le16 word0 /* word0 */;
        __le16 word1 /* word1 */;
@@ -1761,36 +2039,48 @@ struct mstorm_core_conn_ag_ctx {
        __le32 reg1 /* reg1 */;
 };

+
 /*
  * per encapsulation type enabling flags
  */
 struct prs_reg_encapsulation_type_en {
        u8 flags;
+/* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */
 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK     0x1
 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT    0
+/* Enable bit for IP-over-GRE (IP GRE) encapsulation. */
 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK      0x1
 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT     1
+/* Enable bit for VXLAN encapsulation. */
 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK            0x1
 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT           2
+/* Enable bit for T-Tag encapsulation. */
 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK            0x1
 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT           3
+/* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */
 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK  0x1
 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
+/* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */
 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK   0x1
 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT  5
 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                0x3
 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT               6
 };

+
 enum pxp_tph_st_hint {
        TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
        TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
-       TPH_ST_HINT_TARGET
-           /* Device Write and Host Read, or Host Write and Device Read */,
+/* Device Write and Host Read, or Host Write and Device Read */
+       TPH_ST_HINT_TARGET,
+/* Device Write and Host Read, or Host Write and Device Read - with temporal
+ * reuse
+ */
        TPH_ST_HINT_TARGET_PRIO,
        MAX_PXP_TPH_ST_HINT
 };

+
 /*
  * QM hardware structure of enable bypass credit mask
  */
@@ -1814,6 +2104,7 @@ struct qm_rf_bypass_mask {
 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
 };

+
 /*
  * QM hardware structure of opportunistic credit mask
  */
@@ -1841,83 +2132,95 @@ struct qm_rf_opportunistic_mask {
 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT  9
 };

+
 /*
  * QM hardware structure of QM map memory
  */
 struct qm_rf_pq_map {
        __le32 reg;
-#define QM_RF_PQ_MAP_PQ_VALID_MASK          0x1
+#define QM_RF_PQ_MAP_PQ_VALID_MASK          0x1 /* PQ active */
 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT         0
-#define QM_RF_PQ_MAP_RL_ID_MASK             0xFF
+#define QM_RF_PQ_MAP_RL_ID_MASK             0xFF /* RL ID */
 #define QM_RF_PQ_MAP_RL_ID_SHIFT            1
+/* the first PQ associated with the VPORT and VOQ of this PQ */
 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK          0x1FF
 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT         9
-#define QM_RF_PQ_MAP_VOQ_MASK               0x1F
+#define QM_RF_PQ_MAP_VOQ_MASK               0x1F /* VOQ */
 #define QM_RF_PQ_MAP_VOQ_SHIFT              18
-#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK  0x3
+#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK  0x3 /* WRR weight */
 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
-#define QM_RF_PQ_MAP_RL_VALID_MASK          0x1
+#define QM_RF_PQ_MAP_RL_VALID_MASK          0x1 /* RL active */
 #define QM_RF_PQ_MAP_RL_VALID_SHIFT         25
 #define QM_RF_PQ_MAP_RESERVED_MASK          0x3F
 #define QM_RF_PQ_MAP_RESERVED_SHIFT         26
 };

+
 /*
  * Completion params for aggregated interrupt completion
  */
 struct sdm_agg_int_comp_params {
        __le16 params;
+/* the number of aggregated interrupt, 0-31 */
 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
+/* 1 - set a bit in aggregated vector, 0 - dont set */
 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
+/* Number of bit in the aggregated vector, 0-279 (TBD) */
 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
 };

+
 /*
  * SDM operation gen command (generate aggregative interrupt)
  */
 struct sdm_op_gen {
        __le32 command;
+/* completion parameters 0-15 */
 #define SDM_OP_GEN_COMP_PARAM_MASK  0xFFFF
 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
-#define SDM_OP_GEN_COMP_TYPE_MASK   0xF
+#define SDM_OP_GEN_COMP_TYPE_MASK   0xF /* completion type 16-19 */
 #define SDM_OP_GEN_COMP_TYPE_SHIFT  16
-#define SDM_OP_GEN_RESERVED_MASK    0xFFF
+#define SDM_OP_GEN_RESERVED_MASK    0xFFF /* reserved 20-31 */
 #define SDM_OP_GEN_RESERVED_SHIFT   20
 };

+
+
+
+
 struct ystorm_core_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
-#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1
+#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
-#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1
+#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
-#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3
+#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
-#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3
+#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
-#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3
+#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
        u8 flags1;
-#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1
+#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
-#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1
+#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
-#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1
+#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
-#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1
+#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1
+#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1
+#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1
+#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1
+#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
        u8 byte2 /* byte2 */;
        u8 byte3 /* byte3 */;
diff --git a/drivers/net/qede/base/ecore_hsi_eth.h 
b/drivers/net/qede/base/ecore_hsi_eth.h
index 5892f99..e26c183 100644
--- a/drivers/net/qede/base/ecore_hsi_eth.h
+++ b/drivers/net/qede/base/ecore_hsi_eth.h
@@ -38,210 +38,306 @@ struct xstorm_eth_conn_ag_ctx {
        u8 reserved0 /* cdu_validation */;
        u8 eth_state /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
+/* exist_in_qm1 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT              1
+/* exist_in_qm2 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT              2
+/* exist_in_qm3 */
 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
+/* bit4 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT              4
+/* cf_array_active */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT              5
+/* bit6 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT              6
+/* bit7 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT              7
        u8 flags1;
+/* bit8 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT              0
+/* bit9 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT              1
+/* bit10 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK               0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT              2
+/* bit11 */
 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT                  3
+/* bit12 */
 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT                  4
+/* bit13 */
 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT                  5
+/* bit14 */
 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1
 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
+/* bit15 */
 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
        u8 flags2;
+/* timer0cf */
 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                    0
+/* timer1cf */
 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                    2
+/* timer2cf */
 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    4
+/* timer_stop_all */
 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    6
        u8 flags3;
+/* cf4 */
 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                    0
+/* cf5 */
 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                    2
+/* cf6 */
 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                    4
+/* cf7 */
 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                    6
        u8 flags4;
+/* cf8 */
 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                    0
+/* cf9 */
 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK                     0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                    2
+/* cf10 */
 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK                    0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT                   4
+/* cf11 */
 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK                    0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT                   6
        u8 flags5;
+/* cf12 */
 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK                    0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT                   0
+/* cf13 */
 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK                    0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT                   2
+/* cf14 */
 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK                    0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT                   4
+/* cf15 */
 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK                    0x3
 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT                   6
        u8 flags6;
+/* cf16 */
 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3
 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
+/* cf_array_cf */
 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
+/* cf18 */
 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                   0x3
 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                  4
+/* cf19 */
 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
        u8 flags7;
+/* cf20 */
 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK                0x3
 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
+/* cf21 */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK              0x3
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT             2
+/* cf22 */
 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK               0x3
 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT              4
+/* cf0en */
 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                  6
+/* cf1en */
 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                  7
        u8 flags8;
+/* cf2en */
 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  0
+/* cf3en */
 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  1
+/* cf4en */
 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT                  2
+/* cf5en */
 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT                  3
+/* cf6en */
 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT                  4
+/* cf7en */
 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT                  5
+/* cf8en */
 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT                  6
+/* cf9en */
 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK                   0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT                  7
        u8 flags9;
+/* cf10en */
 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                  0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                 0
+/* cf11en */
 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                  0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                 1
+/* cf12en */
 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                  0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                 2
+/* cf13en */
 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                  0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                 3
+/* cf14en */
 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                  0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                 4
+/* cf15en */
 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                  0x1
 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                 5
+/* cf16en */
 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1
 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
+/* cf_array_cf_en */
 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
        u8 flags10;
+/* cf18en */
 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
+/* cf19en */
 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
+/* cf20en */
 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
+/* cf21en */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK              0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT             3
+/* cf22en */
 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
+/* cf23en */
 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1
 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
+/* rule0en */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK              0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT             6
+/* rule1en */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK              0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT             7
        u8 flags11;
+/* rule2en */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK              0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT             0
+/* rule3en */
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK              0x1
 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT             1
+/* rule4en */
 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1
 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
+/* rule5en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                3
+/* rule6en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                4
+/* rule7en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                5
+/* rule8en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
+/* rule9en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK                 0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT                7
        u8 flags12;
+/* rule10en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT               0
+/* rule11en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT               1
+/* rule12en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
+/* rule13en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
+/* rule14en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT               4
+/* rule15en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT               5
+/* rule16en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT               6
+/* rule17en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT               7
        u8 flags13;
+/* rule18en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT               0
+/* rule19en */
 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK                0x1
 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT               1
+/* rule20en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
+/* rule21en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
+/* rule22en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
+/* rule23en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
+/* rule24en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
+/* rule25en */
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
        u8 flags14;
+/* bit16 */
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
+/* bit17 */
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
+/* bit18 */
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
+/* bit19 */
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1
 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
+/* bit20 */
 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1
 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
+/* bit21 */
 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
+/* cf23 */
 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK              0x3
 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
        u8 edpm_event_id /* byte2 */;
@@ -308,31 +404,41 @@ struct ystorm_eth_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 state /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK                  0x1
 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                 0
+/* exist_in_qm1 */
 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK                  0x1
 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                 1
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK     0x3
+#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK     0x3 /* cf0 */
 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT    2
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK      0x3
+#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK      0x3 /* cf1 */
 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT     4
-#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3
+#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3 /* cf2 */
 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                  6
        u8 flags1;
+/* cf0en */
 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK  0x1
 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
+/* cf1en */
 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK   0x1
 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT  1
+/* cf2en */
 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                 0x1
 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                2
+/* rule0en */
 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK               0x1
 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT              3
+/* rule1en */
 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK               0x1
 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT              4
+/* rule2en */
 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK               0x1
 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT              5
+/* rule3en */
 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK               0x1
 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT              6
+/* rule4en */
 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK               0x1
 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT              7
        u8 tx_q0_int_coallecing_timeset /* byte2 */;
@@ -352,84 +458,84 @@ struct tstorm_eth_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
-#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK      0x1
+#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK      0x1 /* exist_in_qm0 */
 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT     0
-#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK      0x1
+#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK      0x1 /* exist_in_qm1 */
 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT     1
-#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK      0x1
+#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK      0x1 /* bit2 */
 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT     2
-#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK      0x1
+#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK      0x1 /* bit3 */
 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT     3
-#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK      0x1
+#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK      0x1 /* bit4 */
 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT     4
-#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK      0x1
+#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK      0x1 /* bit5 */
 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT     5
-#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK       0x3 /* timer0cf */
 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT      6
        u8 flags1;
-#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK       0x3 /* timer1cf */
 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT      0
-#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK       0x3 /* timer2cf */
 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT      2
-#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK       0x3 /* timer_stop_all */
 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT      4
-#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK       0x3 /* cf4 */
 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT      6
        u8 flags2;
-#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK       0x3 /* cf5 */
 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT      0
-#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK       0x3 /* cf6 */
 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT      2
-#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK       0x3 /* cf7 */
 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT      4
-#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK       0x3 /* cf8 */
 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT      6
        u8 flags3;
-#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK       0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK       0x3 /* cf9 */
 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT      0
-#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK      0x3
+#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK      0x3 /* cf10 */
 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT     2
-#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK     0x1 /* cf0en */
 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT    4
-#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK     0x1 /* cf1en */
 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT    5
-#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK     0x1 /* cf2en */
 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT    6
-#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK     0x1 /* cf3en */
 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT    7
        u8 flags4;
-#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK     0x1 /* cf4en */
 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT    0
-#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK     0x1 /* cf5en */
 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT    1
-#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK     0x1 /* cf6en */
 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT    2
-#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK     0x1 /* cf7en */
 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT    3
-#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK     0x1 /* cf8en */
 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT    4
-#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK     0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK     0x1 /* cf9en */
 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT    5
-#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK    0x1
+#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK    0x1 /* cf10en */
 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT   6
-#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK   0x1 /* rule0en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT  7
        u8 flags5;
-#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK   0x1 /* rule1en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT  0
-#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK   0x1 /* rule2en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT  1
-#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK   0x1 /* rule3en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT  2
-#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK   0x1 /* rule4en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT  3
-#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK   0x1 /* rule5en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT  4
-#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK  0x1
+#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK  0x1 /* rule6en */
 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK   0x1 /* rule7en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT  6
-#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK   0x1
+#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK   0x1 /* rule8en */
 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT  7
        __le32 reg0 /* reg0 */;
        __le32 reg1 /* reg1 */;
@@ -456,57 +562,82 @@ struct ustorm_eth_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK                    0x1
 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                   0
+/* exist_in_qm1 */
 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK                    0x1
 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                   1
+/* timer0cf */
 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK     0x3
 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT    2
+/* timer1cf */
 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK     0x3
 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT    4
+/* timer2cf */
 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3
 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    6
        u8 flags1;
+/* timer_stop_all */
 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    0
+/* cf4 */
 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK               0x3
 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT              2
+/* cf5 */
 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK               0x3
 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT              4
+/* cf6 */
 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK       0x3
 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT      6
        u8 flags2;
+/* cf0en */
 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK  0x1
 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
+/* cf1en */
 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK  0x1
 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
+/* cf2en */
 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1
 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  2
+/* cf3en */
 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1
 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  3
+/* cf4en */
 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK            0x1
 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT           4
+/* cf5en */
 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK            0x1
 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT           5
+/* cf6en */
 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK    0x1
 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT   6
+/* rule0en */
 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                7
        u8 flags3;
+/* rule1en */
 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                0
+/* rule2en */
 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                1
+/* rule3en */
 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                2
+/* rule4en */
 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                3
+/* rule5en */
 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                4
+/* rule6en */
 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                5
+/* rule7en */
 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                6
+/* rule8en */
 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK                 0x1
 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT                7
        u8 byte2 /* byte2 */;
@@ -539,83 +670,79 @@ struct mstorm_eth_conn_st_ctx {
  * eth connection context
  */
 struct eth_conn_context {
-       struct tstorm_eth_conn_st_ctx tstorm_st_context
-           /* tstorm storm context */;
+/* tstorm storm context */
+       struct tstorm_eth_conn_st_ctx tstorm_st_context;
        struct regpair tstorm_st_padding[2] /* padding */;
-       struct pstorm_eth_conn_st_ctx pstorm_st_context
-           /* pstorm storm context */;
-       struct xstorm_eth_conn_st_ctx xstorm_st_context
-           /* xstorm storm context */;
-       struct xstorm_eth_conn_ag_ctx xstorm_ag_context
-           /* xstorm aggregative context */;
-       struct ystorm_eth_conn_st_ctx ystorm_st_context
-           /* ystorm storm context */;
-       struct ystorm_eth_conn_ag_ctx ystorm_ag_context
-           /* ystorm aggregative context */;
-       struct tstorm_eth_conn_ag_ctx tstorm_ag_context
-           /* tstorm aggregative context */;
-       struct ustorm_eth_conn_ag_ctx ustorm_ag_context
-           /* ustorm aggregative context */;
-       struct ustorm_eth_conn_st_ctx ustorm_st_context
-           /* ustorm storm context */;
-       struct mstorm_eth_conn_st_ctx mstorm_st_context
-           /* mstorm storm context */;
+/* pstorm storm context */
+       struct pstorm_eth_conn_st_ctx pstorm_st_context;
+/* xstorm storm context */
+       struct xstorm_eth_conn_st_ctx xstorm_st_context;
+/* xstorm aggregative context */
+       struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
+/* ystorm storm context */
+       struct ystorm_eth_conn_st_ctx ystorm_st_context;
+/* ystorm aggregative context */
+       struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
+/* tstorm aggregative context */
+       struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
+/* ustorm aggregative context */
+       struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
+/* ustorm storm context */
+       struct ustorm_eth_conn_st_ctx ustorm_st_context;
+/* mstorm storm context */
+       struct mstorm_eth_conn_st_ctx mstorm_st_context;
 };

+
 /*
  * Ethernet filter types: mac/vlan/pair
  */
 enum eth_error_code {
        ETH_OK = 0x00 /* command succeeded */,
-       ETH_FILTERS_MAC_ADD_FAIL_FULL
-           /* mac add filters command failed due to cam full state */,
-       ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2
-           /* mac add filters command failed due to mtt2 full state */,
-       ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2
-           /* mac add filters command failed due to duplicate mac address */,
-       ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2
-           /* mac add filters command failed due to duplicate mac address */,
-       ETH_FILTERS_MAC_DEL_FAIL_NOF
-           /* mac delete filters command failed due to not found state */,
-       ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2
-           /* mac delete filters command failed due to not found state */,
-       ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2
-           /* mac delete filters command failed due to not found state */,
-       ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC
-           /* mac add filters command failed due to MAC Address of
-            * 00:00:00:00:00:00
-            */
-           ,
-       ETH_FILTERS_VLAN_ADD_FAIL_FULL
-           /* vlan add filters command failed due to cam full state */,
-       ETH_FILTERS_VLAN_ADD_FAIL_DUP
-           /* vlan add filters command failed due to duplicate VLAN filter */,
-       ETH_FILTERS_VLAN_DEL_FAIL_NOF
-           /* vlan delete filters command failed due to not found state */,
-       ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1
-           /* vlan delete filters command failed due to not found state */,
-       ETH_FILTERS_PAIR_ADD_FAIL_DUP
-           /* pair add filters command failed due to duplicate request */,
-       ETH_FILTERS_PAIR_ADD_FAIL_FULL
-           /* pair add filters command failed due to full state */,
-       ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC
-           /* pair add filters command failed due to full state */,
-       ETH_FILTERS_PAIR_DEL_FAIL_NOF
-           /* pair add filters command failed due not found state */,
-       ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1
-           /* pair add filters command failed due not found state */,
-       ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC
-           /* pair add filters command failed due to MAC Address of
-            * 00:00:00:00:00:00
-            */
-           ,
-       ETH_FILTERS_VNI_ADD_FAIL_FULL
-           /* vni add filters command failed due to cam full state */,
-       ETH_FILTERS_VNI_ADD_FAIL_DUP
-           /* vni add filters command failed due to duplicate VNI filter */,
+/* mac add filters command failed due to cam full state */
+       ETH_FILTERS_MAC_ADD_FAIL_FULL,
+/* mac add filters command failed due to mtt2 full state */
+       ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
+/* mac add filters command failed due to duplicate mac address */
+       ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
+/* mac add filters command failed due to duplicate mac address */
+       ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
+/* mac delete filters command failed due to not found state */
+       ETH_FILTERS_MAC_DEL_FAIL_NOF,
+/* mac delete filters command failed due to not found state */
+       ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
+/* mac delete filters command failed due to not found state */
+       ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
+/* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */
+       ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
+/* vlan add filters command failed due to cam full state */
+       ETH_FILTERS_VLAN_ADD_FAIL_FULL,
+/* vlan add filters command failed due to duplicate VLAN filter */
+       ETH_FILTERS_VLAN_ADD_FAIL_DUP,
+/* vlan delete filters command failed due to not found state */
+       ETH_FILTERS_VLAN_DEL_FAIL_NOF,
+/* vlan delete filters command failed due to not found state */
+       ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
+/* pair add filters command failed due to duplicate request */
+       ETH_FILTERS_PAIR_ADD_FAIL_DUP,
+/* pair add filters command failed due to full state */
+       ETH_FILTERS_PAIR_ADD_FAIL_FULL,
+/* pair add filters command failed due to full state */
+       ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
+/* pair add filters command failed due not found state */
+       ETH_FILTERS_PAIR_DEL_FAIL_NOF,
+/* pair add filters command failed due not found state */
+       ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
+/* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */
+       ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
+/* vni add filters command failed due to cam full state */
+       ETH_FILTERS_VNI_ADD_FAIL_FULL,
+/* vni add filters command failed due to duplicate VNI filter */
+       ETH_FILTERS_VNI_ADD_FAIL_DUP,
        MAX_ETH_ERROR_CODE
 };

+
 /*
  * opcodes for the event ring
  */
@@ -640,6 +767,7 @@ enum eth_event_opcode {
        MAX_ETH_EVENT_OPCODE
 };

+
 /*
  * Classify rule types in E2/E3
  */
@@ -647,11 +775,12 @@ enum eth_filter_action {
        ETH_FILTER_ACTION_UNUSED,
        ETH_FILTER_ACTION_REMOVE,
        ETH_FILTER_ACTION_ADD,
-       ETH_FILTER_ACTION_REMOVE_ALL
-           /* Remove all filters of given type and vport ID. */,
+/* Remove all filters of given type and vport ID. */
+       ETH_FILTER_ACTION_REMOVE_ALL,
        MAX_ETH_FILTER_ACTION
 };

+
 /*
  * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
  */
@@ -667,6 +796,7 @@ struct eth_filter_cmd {
        __le16 vlan_id;
 };

+
 /*
  *  $$KEEP_ENDIANNESS$$
  */
@@ -674,10 +804,14 @@ struct eth_filter_cmd_header {
        u8 rx /* If set, apply these commands to the RX path */;
        u8 tx /* If set, apply these commands to the TX path */;
        u8 cmd_cnt /* Number of filter commands */;
+/* 0 - dont assert in case of filter configuration error. Just return an error
+ * code. 1 - assert in case of filter configuration error.
+ */
        u8 assert_on_error;
        u8 reserved1[4];
 };

+
 /*
  * Ethernet filter types: mac/vlan/pair
  */
@@ -689,25 +823,27 @@ enum eth_filter_type {
        ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
        ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
        ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
-       ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */
-           ,
+/* Add/remove a inner MAC-VNI pair */
+       ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
        ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
        ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
        MAX_ETH_FILTER_TYPE
 };

+
 /*
  * eth IPv4 Fragment Type
  */
 enum eth_ipv4_frag_type {
        ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
-       ETH_IPV4_FIRST_FRAG
-           /* First Fragment of IPv4 Packet (contains headers) */,
-       ETH_IPV4_NON_FIRST_FRAG
-           /* Non-First Fragment of IPv4 Packet (does not contain headers) */,
+/* First Fragment of IPv4 Packet (contains headers) */
+       ETH_IPV4_FIRST_FRAG,
+/* Non-First Fragment of IPv4 Packet (does not contain headers) */
+       ETH_IPV4_NON_FIRST_FRAG,
        MAX_ETH_IPV4_FRAG_TYPE
 };

+
 /*
  * eth IPv4 Fragment Type
  */
@@ -717,6 +853,7 @@ enum eth_ip_type {
        MAX_ETH_IP_TYPE
 };

+
 /*
  * Ethernet Ramrod Command IDs
  */
@@ -747,73 +884,101 @@ enum eth_ramrod_cmd_id {
        MAX_ETH_RAMROD_CMD_ID
 };

+
 /*
  * return code from eth sp ramrods
  */
 struct eth_return_code {
        u8 value;
+/* error code (use enum eth_error_code) */
 #define ETH_RETURN_CODE_ERR_CODE_MASK  0x1F
 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
 #define ETH_RETURN_CODE_RESERVED_MASK  0x3
 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
+/* rx path - 0, tx path - 1 */
 #define ETH_RETURN_CODE_RX_TX_MASK     0x1
 #define ETH_RETURN_CODE_RX_TX_SHIFT    7
 };

+
 /*
  * What to do in case an error occurs
  */
 enum eth_tx_err {
        ETH_TX_ERR_DROP /* Drop erroneous packet. */,
-       ETH_TX_ERR_ASSERT_MALICIOUS
-           /* Assert an interrupt for PF, declare as malicious for VF */,
+/* Assert an interrupt for PF, declare as malicious for VF */
+       ETH_TX_ERR_ASSERT_MALICIOUS,
        MAX_ETH_TX_ERR
 };

+
 /*
  * Array of the different error type behaviors
  */
 struct eth_tx_err_vals {
        __le16 values;
+/* Wrong VLAN insertion mode (use enum eth_tx_err) */
 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK            0x1
 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT           0
+/* Packet is below minimal size (use enum eth_tx_err) */
 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK             0x1
 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT            1
+/* Vport has sent spoofed packet (use enum eth_tx_err) */
 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK            0x1
 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT           2
+/* Packet with illegal type of inband tag (use enum eth_tx_err) */
 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK          0x1
 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT         3
+/* Packet marked for VLAN insertion when inband tag is present
+ * (use enum eth_tx_err)
+ */
 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK  0x1
 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
+/* Non LSO packet larger than MTU (use enum eth_tx_err) */
 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK                0x1
 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT               5
+/* VF/PF has sent LLDP/PFC or any other type of control packet which is not
+ * allowed to (use enum eth_tx_err)
+ */
 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK        0x1
 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT       6
 #define ETH_TX_ERR_VALS_RESERVED_MASK                     0x1FF
 #define ETH_TX_ERR_VALS_RESERVED_SHIFT                    7
 };

+
 /*
  * vport rss configuration data
  */
 struct eth_vport_rss_config {
        __le16 capabilities;
+/* configuration of the IpV4 2-tuple capability */
 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK        0x1
 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT       0
+/* configuration of the IpV6 2-tuple capability */
 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK        0x1
 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT       1
+/* configuration of the IpV4 4-tuple capability for TCP */
 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK    0x1
 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT   2
+/* configuration of the IpV6 4-tuple capability for TCP */
 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK    0x1
 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT   3
+/* configuration of the IpV4 4-tuple capability for UDP */
 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK    0x1
 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT   4
+/* configuration of the IpV6 4-tuple capability for UDP */
 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK    0x1
 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT   5
+/* configuration of the 5-tuple capability */
 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK  0x1
 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
+/* if set update the rss keys */
 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK              0x1FF
 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT             7
+/* The RSS engine ID. Must be allocated to each vport with RSS enabled.
+ * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type.
+ */
        u8 rss_id;
        u8 rss_mode /* The RSS mode for this function */;
        u8 update_rss_key /* if set update the rss key */;
@@ -821,13 +986,14 @@ struct eth_vport_rss_config {
        u8 update_rss_capabilities /* if set update the capabilities */;
        u8 tbl_size /* rss mask (Tbl size) */;
        __le32 reserved2[2];
-       __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]
-           /* RSS indirection table */;
-       __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */
-          ;
+/* RSS indirection table */
+       __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
+/* RSS key supplied to us by OS */
+       __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
        __le32 reserved3[2];
 };

+
 /*
  * eth vport RSS mode
  */
@@ -837,21 +1003,28 @@ enum eth_vport_rss_mode {
        MAX_ETH_VPORT_RSS_MODE
 };

+
 /*
  * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
  */
 struct eth_vport_rx_mode {
        __le16 state;
+/* drop all unicast packets */
 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK          0x1
 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT         0
+/* accept all unicast packets (subject to vlan) */
 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK        0x1
 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT       1
+/* accept all unmatched unicast packets */
 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK  0x1
 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
+/* drop all multicast packets */
 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK          0x1
 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT         3
+/* accept all multicast packets (subject to vlan) */
 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK        0x1
 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT       4
+/* accept all broadcast packets (subject to vlan) */
 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK        0x1
 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT       5
 #define ETH_VPORT_RX_MODE_RESERVED1_MASK               0x3FF
@@ -859,6 +1032,7 @@ struct eth_vport_rx_mode {
        __le16 reserved2[3];
 };

+
 /*
  * Command for setting tpa parameters
  */
@@ -867,39 +1041,45 @@ struct eth_vport_tpa_param {
        u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
        u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
        u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
+/* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment
+ * allowed
+ */
        u8 tpa_pkt_split_flg;
-       u8 tpa_hdr_data_split_flg
-           /* If set, put header of first TPA segment on bd and data on SGE */
-          ;
-       u8 tpa_gro_consistent_flg
-           /* If set, GRO data consistent will checked for TPA continue */;
-       u8 tpa_max_aggs_num
-           /* maximum number of opened aggregations per v-port  */;
+/* If set, put header of first TPA segment on bd and data on SGE */
+       u8 tpa_hdr_data_split_flg;
+/* If set, GRO data consistent will checked for TPA continue */
+       u8 tpa_gro_consistent_flg;
+/* maximum number of opened aggregations per v-port  */
+       u8 tpa_max_aggs_num;
        __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
-       __le16 tpa_min_size_to_start
-           /* minimum TCP payload size for a packet to start aggregation */;
-       __le16 tpa_min_size_to_cont
-           /* minimum TCP payload size for a packet to continue aggregation */
-          ;
-       u8 max_buff_num
-           /* maximal number of buffers that can be used for one aggregation */
-          ;
+/* minimum TCP payload size for a packet to start aggregation */
+       __le16 tpa_min_size_to_start;
+/* minimum TCP payload size for a packet to continue aggregation */
+       __le16 tpa_min_size_to_cont;
+/* maximal number of buffers that can be used for one aggregation */
+       u8 max_buff_num;
        u8 reserved;
 };

+
 /*
  * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
  */
 struct eth_vport_tx_mode {
        __le16 state;
+/* drop all unicast packets */
 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK    0x1
 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT   0
+/* accept all unicast packets (subject to vlan) */
 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK  0x1
 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
+/* drop all multicast packets */
 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK    0x1
 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT   2
+/* accept all multicast packets (subject to vlan) */
 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK  0x1
 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
+/* accept all broadcast packets (subject to vlan) */
 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK  0x1
 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
 #define ETH_VPORT_TX_MODE_RESERVED1_MASK         0x7FF
@@ -907,6 +1087,7 @@ struct eth_vport_tx_mode {
        __le16 reserved2[3];
 };

+
 /*
  * Ramrod data for rx create gft action
  */
@@ -916,6 +1097,7 @@ enum gft_filter_update_action {
        MAX_GFT_FILTER_UPDATE_ACTION
 };

+
 /*
  * Ramrod data for rx create gft action
  */
@@ -925,6 +1107,9 @@ enum gft_logic_filter_type {
        MAX_GFT_LOGIC_FILTER_TYPE
 };

+
+
+
 /*
  * Ramrod data for rx add openflow filter
  */
@@ -933,10 +1118,12 @@ struct rx_add_openflow_filter_data {
        u8 priority /* Searcher String - Packet priority */;
        u8 reserved0;
        __le32 tenant_id /* Searcher String - Tenant ID */;
-       __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */;
-       __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */
-          ;
-       __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */;
+/* Searcher String - Destination Mac Bytes 0 to 1 */
+       __le16 dst_mac_hi;
+/* Searcher String - Destination Mac Bytes 2 to 3 */
+       __le16 dst_mac_mid;
+/* Searcher String - Destination Mac Bytes 4 to 5 */
+       __le16 dst_mac_lo;
        __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
        __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
        __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
@@ -952,6 +1139,7 @@ struct rx_add_openflow_filter_data {
        __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
 };

+
 /*
  * Ramrod data for rx create gft action
  */
@@ -960,6 +1148,7 @@ struct rx_create_gft_action_data {
        u8 reserved[7];
 };

+
 /*
  * Ramrod data for rx create openflow action
  */
@@ -968,6 +1157,7 @@ struct rx_create_openflow_action_data {
        u8 reserved[7];
 };

+
 /*
  * Ramrod data for rx queue start ramrod
  */
@@ -984,16 +1174,19 @@ struct rx_queue_start_ramrod_data {
        u8 stats_counter_id /* Statistics counter ID */;
        u8 pin_context /* Pin context in CCFC to improve performance */;
        u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
-       u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */
-          ;
-       u8 pxp_st_hint
-           /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */;
+/* PXP command TPH Valid - for packet placement */
+       u8 pxp_tph_valid_pkt;
+/* PXP command Steering tag hint. Use enum pxp_tph_st_hint */
+       u8 pxp_st_hint;
        __le16 pxp_st_index /* PXP command Steering tag index */;
-       u8 pmd_mode
-           /* Indicates that current queue belongs to poll-mode driver */;
+/* Indicates that current queue belongs to poll-mode driver */
+       u8 pmd_mode;
+/* Indicates that the current queue is using the TX notification queue
+ * mechanism - should be set only for PMD queue
+ */
        u8 notify_en;
-       u8 toggle_val
-           /* Initial value for the toggle valid bit - used in PMD mode */;
+/* Initial value for the toggle valid bit - used in PMD mode */
+       u8 toggle_val;
 /* Index of RX producers in VF zone. Used for VF only. */
        u8 vf_rx_prod_index;
 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
@@ -1007,6 +1200,7 @@ struct rx_queue_start_ramrod_data {
        struct regpair reserved2 /* FW reserved. */;
 };

+
 /*
  * Ramrod data for rx queue stop ramrod
  */
@@ -1018,6 +1212,7 @@ struct rx_queue_stop_ramrod_data {
        u8 reserved[3];
 };

+
 /*
  * Ramrod data for rx queue update ramrod
  */
@@ -1035,6 +1230,7 @@ struct rx_queue_update_ramrod_data {
        struct regpair reserved6 /* FW reserved. */;
 };

+
 /*
  * Ramrod data for rx Add UDP Filter
  */
@@ -1044,17 +1240,16 @@ struct rx_udp_filter_data {
        u8 ip_type /* Searcher String - IP Type */;
        u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
        __le16 reserved1;
+/* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only 
*/
        __le32 ip_dst_addr[4];
-           /* Searcher String-IP Dest Addr for IPv4 use ip_dst_addr[0] only */
-          ;
-       __le32 ip_src_addr[4]
-           /* Searcher String-IP Src Addr, for IPv4 use ip_dst_addr[0] only */
-          ;
+/* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */
+       __le32 ip_src_addr[4];
        __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
        __le16 udp_src_port /* Searcher String - UDP Source Port */;
        __le32 tenant_id /* Searcher String - Tenant ID */;
 };

+
 /*
  * Ramrod to add filter - filter is packet headr of type of packet wished to
  * pass certin FW flow
@@ -1075,6 +1270,8 @@ struct rx_update_gft_filter_data {
        u8 reserved;
 };

+
+
 /*
  * Ramrod data for tx queue start ramrod
  */
@@ -1086,16 +1283,26 @@ struct tx_queue_start_ramrod_data {
        u8 stats_counter_id /* Statistics counter ID to use */;
        __le16 qm_pq_id /* QM PQ ID */;
        u8 flags;
+/* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */
 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK  0x1
 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
+/* If set, Test Mode - packets will be duplicated by Xstorm handler */
 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK      0x1
 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT     1
+/* If set, Test Mode - packets destination will be determined by dest_port_mode
+ * field from Tx BD
+ */
 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK      0x1
 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT     2
+/* Indicates that current queue belongs to poll-mode driver */
 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK               0x1
 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT              3
+/* Indicates that the current queue is using the TX notification queue
+ * mechanism - should be set only for PMD queue
+ */
 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK              0x1
 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT             4
+/* Pin context in CCFC to improve performance */
 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK            0x1
 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT           5
 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK              0x3
@@ -1104,12 +1311,13 @@ struct tx_queue_start_ramrod_data {
        u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
        u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
        __le16 pxp_st_index /* PXP command Steering tag index */;
-       __le16 comp_agg_size /* TX completion min agg size - for PMD queues */;
+/* TX completion min agg size - for PMD queues */
+       __le16 comp_agg_size;
        __le16 queue_zone_id /* queue zone ID to use */;
        __le16 reserved2 /* FW reserved. (test_dup_count) */;
        __le16 pbl_size /* Number of BD pages pointed by PBL */;
-       __le16 tx_queue_id
-           /* unique Queue ID - currently used only by PMD flow */;
+/* unique Queue ID - currently used only by PMD flow */
+       __le16 tx_queue_id;
 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
  * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
  * available)
@@ -1117,10 +1325,11 @@ struct tx_queue_start_ramrod_data {
        __le16 same_as_last_id;
        __le16 reserved[3];
        struct regpair pbl_base_addr /* address of the pbl page */;
-       struct regpair bd_cons_address
-           /* BD consumer address in host - for PMD queues */;
+/* BD consumer address in host - for PMD queues */
+       struct regpair bd_cons_address;
 };

+
 /*
  * Ramrod data for tx queue stop ramrod
  */
@@ -1128,16 +1337,19 @@ struct tx_queue_stop_ramrod_data {
        __le16 reserved[4];
 };

+
+
 /*
  * Ramrod data for vport update ramrod
  */
 struct vport_filter_update_ramrod_data {
-       struct eth_filter_cmd_header filter_cmd_hdr
-           /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */;
-       struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]
-           /* Filter Commands */;
+/* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */
+       struct eth_filter_cmd_header filter_cmd_hdr;
+/* Filter Commands */
+       struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
 };

+
 /*
  * Ramrod data for vport start ramrod
  */
@@ -1149,21 +1361,26 @@ struct vport_start_ramrod_data {
        u8 inner_vlan_removal_en;
        struct eth_vport_rx_mode rx_mode /* Rx filter data */;
        struct eth_vport_tx_mode tx_mode /* Tx filter data */;
-       struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */
-          ;
+/* TPA configuration parameters */
+       struct eth_vport_tpa_param tpa_param;
        __le16 default_vlan /* Default Vlan value to be forced by FW */;
        u8 tx_switching_en /* Tx switching is enabled for current Vport */;
-       u8 anti_spoofing_en
-           /* Anti-spoofing verification is set for current Vport */;
-       u8 default_vlan_en
-           /* If set, the default Vlan value is forced by the FW */;
-       u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
-          ;
+/* Anti-spoofing verification is set for current Vport */
+       u8 anti_spoofing_en;
+/* If set, the default Vlan value is forced by the FW */
+       u8 default_vlan_en;
+/* If set, the vport handles PTP Timesync Packets */
+       u8 handle_ptp_pkts;
+/* If enable then innerVlan will be striped and not written to cqe */
        u8 silent_vlan_removal_en;
-       /* If enable then innerVlan will be striped and not written to cqe */
+/* If set untagged filter (vlan0) is added to current Vport, otherwise port is
+ * marked as any-vlan
+ */
        u8 untagged;
-       struct eth_tx_err_vals tx_err_behav
-           /* Desired behavior per TX error type */;
+/* Desired behavior per TX error type */
+       struct eth_tx_err_vals tx_err_behav;
+/* If set, ETH header padding will not inserted. placement_offset will be zero.
+ */
        u8 zero_placement_offset;
 /* If set, Contorl frames will be filtered according to MAC check. */
        u8 ctl_frame_mac_check_en;
@@ -1172,6 +1389,7 @@ struct vport_start_ramrod_data {
        u8 reserved[5];
 };

+
 /*
  * Ramrod data for vport stop ramrod
  */
@@ -1180,6 +1398,7 @@ struct vport_stop_ramrod_data {
        u8 reserved[7];
 };

+
 /*
  * Ramrod data for vport update ramrod
  */
@@ -1191,37 +1410,41 @@ struct vport_update_ramrod_data_cmn {
        u8 tx_active_flg /* tx active flag value */;
        u8 update_rx_mode_flg /* set if rx state data should be handled */;
        u8 update_tx_mode_flg /* set if tx state data should be handled */;
-       u8 update_approx_mcast_flg
-           /* set if approx. mcast data should be handled */;
+/* set if approx. mcast data should be handled */
+       u8 update_approx_mcast_flg;
        u8 update_rss_flg /* set if rss data should be handled  */;
-       u8 update_inner_vlan_removal_en_flg
-           /* set if inner_vlan_removal_en should be handled */;
+/* set if inner_vlan_removal_en should be handled */
+       u8 update_inner_vlan_removal_en_flg;
        u8 inner_vlan_removal_en;
+/* set if tpa parameters should be handled, TPA must be disable before */
        u8 update_tpa_param_flg;
        u8 update_tpa_en_flg /* set if tpa enable changes */;
-       u8 update_tx_switching_en_flg
-           /* set if tx switching en flag should be handled */;
+/* set if tx switching en flag should be handled */
+       u8 update_tx_switching_en_flg;
        u8 tx_switching_en /* tx switching en value */;
-       u8 update_anti_spoofing_en_flg
-           /* set if anti spoofing flag should be handled */;
+/* set if anti spoofing flag should be handled */
+       u8 update_anti_spoofing_en_flg;
        u8 anti_spoofing_en /* Anti-spoofing verification en value */;
-       u8 update_handle_ptp_pkts
-           /* set if handle_ptp_pkts should be handled. */;
-       u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
-          ;
-       u8 update_default_vlan_en_flg
-           /* If set, the default Vlan enable flag is updated */;
-       u8 default_vlan_en
-           /* If set, the default Vlan value is forced by the FW */;
-       u8 update_default_vlan_flg
-           /* If set, the default Vlan value is updated */;
+/* set if handle_ptp_pkts should be handled. */
+       u8 update_handle_ptp_pkts;
+/* If set, the vport handles PTP Timesync Packets */
+       u8 handle_ptp_pkts;
+/* If set, the default Vlan enable flag is updated */
+       u8 update_default_vlan_en_flg;
+/* If set, the default Vlan value is forced by the FW */
+       u8 default_vlan_en;
+/* If set, the default Vlan value is updated */
+       u8 update_default_vlan_flg;
        __le16 default_vlan /* Default Vlan value to be forced by FW */;
-       u8 update_accept_any_vlan_flg
-           /* set if accept_any_vlan should be handled */;
+/* set if accept_any_vlan should be handled */
+       u8 update_accept_any_vlan_flg;
        u8 accept_any_vlan /* accept_any_vlan updated value */;
+/* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be 
enabled
+ * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data
+ */
        u8 silent_vlan_removal_en;
-       u8 update_mtu_flg
-           /* If set, MTU will be updated. Vport must be not active. */;
+/* If set, MTU will be updated. Vport must be not active. */
+       u8 update_mtu_flg;
        __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
        u8 reserved[2];
 };
@@ -1234,54 +1457,76 @@ struct vport_update_ramrod_mcast {
  * Ramrod data for vport update ramrod
  */
 struct vport_update_ramrod_data {
-       struct vport_update_ramrod_data_cmn common
-           /* Common data for all vport update ramrods */;
+/* Common data for all vport update ramrods */
+       struct vport_update_ramrod_data_cmn common;
        struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
        struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
-       struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */
-          ;
+/* TPA configuration parameters */
+       struct eth_vport_tpa_param tpa_param;
        struct vport_update_ramrod_mcast approx_mcast;
        struct eth_vport_rss_config rss_config /* rss config data */;
 };

+
+
+
+
+
 /*
  * GFT CAM line struct
  */
 struct gft_cam_line {
        __le32 camline;
+/* Indication if the line is valid. */
 #define GFT_CAM_LINE_VALID_MASK      0x1
 #define GFT_CAM_LINE_VALID_SHIFT     0
+/* Data bits, the word that compared with the profile key */
 #define GFT_CAM_LINE_DATA_MASK       0x3FFF
 #define GFT_CAM_LINE_DATA_SHIFT      1
+/* Mask bits, indicate the bits in the data that are Dont-Care */
 #define GFT_CAM_LINE_MASK_BITS_MASK  0x3FFF
 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
 #define GFT_CAM_LINE_RESERVED1_MASK  0x7
 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
 };

+
 /*
  * GFT CAM line struct (for driversim use)
  */
 struct gft_cam_line_mapped {
        __le32 camline;
+/* Indication if the line is valid. */
 #define GFT_CAM_LINE_MAPPED_VALID_MASK                     0x1
 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT                    0
+/* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK                0x1
 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT               1
+/* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK         0x1
 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT        2
+/* use enum gft_profile_upper_protocol_type
+ * (use enum gft_profile_upper_protocol_type)
+ */
 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK       0xF
 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT      3
+/* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK               0xF
 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT              7
 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK                     0xF
 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT                    11
+/* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK           0x1
 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT          15
+/* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK    0x1
 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT   16
+/* use enum gft_profile_upper_protocol_type
+ * (use enum gft_profile_upper_protocol_type)
+ */
 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK  0xF
 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
+/* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK          0xF
 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT         21
 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK                0xF
@@ -1290,11 +1535,13 @@ struct gft_cam_line_mapped {
 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT                29
 };

+
 union gft_cam_line_union {
        struct gft_cam_line cam_line;
        struct gft_cam_line_mapped cam_line_mapped;
 };

+
 /*
  * Used in gft_profile_key: Indication for ip version
  */
@@ -1304,17 +1551,24 @@ enum gft_profile_ip_version {
        MAX_GFT_PROFILE_IP_VERSION
 };

+
 /*
  * Profile key stucr fot GFT logic in Prs
  */
 struct gft_profile_key {
        __le16 profile_key;
+/* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
 #define GFT_PROFILE_KEY_IP_VERSION_MASK           0x1
 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT          0
+/* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK    0x1
 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT   1
+/* use enum gft_profile_upper_protocol_type
+ * (use enum gft_profile_upper_protocol_type)
+ */
 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK  0xF
 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
+/* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK          0xF
 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT         6
 #define GFT_PROFILE_KEY_PF_ID_MASK                0xF
@@ -1323,6 +1577,7 @@ struct gft_profile_key {
 #define GFT_PROFILE_KEY_RESERVED0_SHIFT           14
 };

+
 /*
  * Used in gft_profile_key: Indication for tunnel type
  */
@@ -1336,6 +1591,7 @@ enum gft_profile_tunnel_type {
        MAX_GFT_PROFILE_TUNNEL_TYPE
 };

+
 /*
  * Used in gft_profile_key: Indication for protocol type
  */
@@ -1359,11 +1615,13 @@ enum gft_profile_upper_protocol_type {
        MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
 };

+
 /*
  * GFT RAM line struct
  */
 struct gft_ram_line {
        __le32 low32bits;
+/*  (use enum gft_vlan_select) */
 #define GFT_RAM_LINE_VLAN_SELECT_MASK              0x3
 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT             0
 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK          0x1
@@ -1451,6 +1709,7 @@ struct gft_ram_line {
 #define GFT_RAM_LINE_RESERVED1_SHIFT               10
 };

+
 /*
  * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
  */
@@ -1462,36 +1721,39 @@ enum gft_vlan_select {
        MAX_GFT_VLAN_SELECT
 };

+
 struct mstorm_eth_conn_ag_ctx {
        u8 byte0 /* cdu_validation */;
        u8 byte1 /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK  0x1
 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+/* exist_in_qm1 */
 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK          0x1
 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT         1
-#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK           0x3
+#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK           0x3 /* cf0 */
 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT          2
-#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK           0x3
+#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK           0x3 /* cf1 */
 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT          4
-#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK           0x3
+#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK           0x3 /* cf2 */
 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT          6
        u8 flags1;
-#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK         0x1
+#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT        0
-#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK         0x1
+#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT        1
-#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK         0x1
+#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK         0x1 /* cf2en */
 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT        2
-#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK       0x1
+#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT      3
-#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK       0x1
+#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT      4
-#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK       0x1
+#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT      5
-#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK       0x1
+#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT      6
-#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK       0x1
+#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT      7
        __le16 word0 /* word0 */;
        __le16 word1 /* word1 */;
@@ -1500,214 +1762,312 @@ struct mstorm_eth_conn_ag_ctx {
 };


+
+
 struct xstormEthConnAgCtxDqExtLdPart {
        u8 reserved0 /* cdu_validation */;
        u8 eth_state /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT           0
+/* exist_in_qm1 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT              1
+/* exist_in_qm2 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT              2
+/* exist_in_qm3 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT           3
+/* bit4 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT              4
+/* cf_array_active */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT              5
+/* bit6 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT              6
+/* bit7 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT              7
        u8 flags1;
+/* bit8 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT              0
+/* bit9 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT              1
+/* bit10 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK               0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT              2
+/* bit11 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT                  3
+/* bit12 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT                  4
+/* bit13 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT                  5
+/* bit14 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK          0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT         6
+/* bit15 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT           7
        u8 flags2;
+/* timer0cf */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT                    0
+/* timer1cf */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT                    2
+/* timer2cf */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT                    4
+/* timer_stop_all */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT                    6
        u8 flags3;
+/* cf4 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT                    0
+/* cf5 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT                    2
+/* cf6 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT                    4
+/* cf7 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT                    6
        u8 flags4;
+/* cf8 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT                    0
+/* cf9 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK                     0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT                    2
+/* cf10 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK                    0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT                   4
+/* cf11 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK                    0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT                   6
        u8 flags5;
+/* cf12 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK                    0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT                   0
+/* cf13 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK                    0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT                   2
+/* cf14 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK                    0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT                   4
+/* cf15 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK                    0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT                   6
        u8 flags6;
+/* cf16 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK        0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT       0
+/* cf_array_cf */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK        0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT       2
+/* cf18 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK                   0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT                  4
+/* cf19 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK            0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT           6
        u8 flags7;
+/* cf20 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK                0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT               0
+/* cf21 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK              0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT             2
+/* cf22 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK               0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT              4
+/* cf0en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT                  6
+/* cf1en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT                  7
        u8 flags8;
+/* cf2en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT                  0
+/* cf3en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT                  1
+/* cf4en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT                  2
+/* cf5en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT                  3
+/* cf6en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT                  4
+/* cf7en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT                  5
+/* cf8en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT                  6
+/* cf9en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK                   0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT                  7
        u8 flags9;
+/* cf10en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK                  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT                 0
+/* cf11en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK                  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT                 1
+/* cf12en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK                  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT                 2
+/* cf13en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK                  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT                 3
+/* cf14en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK                  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT                 4
+/* cf15en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK                  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT                 5
+/* cf16en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK     0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT    6
+/* cf_array_cf_en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK     0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT    7
        u8 flags10;
+/* cf18en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT               0
+/* cf19en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK         0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT        1
+/* cf20en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK             0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT            2
+/* cf21en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK              0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT             3
+/* cf22en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT           4
+/* cf23en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK  0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
+/* rule0en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK              0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT             6
+/* rule1en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK              0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT             7
        u8 flags11;
+/* rule2en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK              0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT             0
+/* rule3en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK              0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT             1
+/* rule4en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK          0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT         2
+/* rule5en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK                 0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT                3
+/* rule6en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK                 0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT                4
+/* rule7en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK                 0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT                5
+/* rule8en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT           6
+/* rule9en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK                 0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT                7
        u8 flags12;
+/* rule10en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT               0
+/* rule11en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT               1
+/* rule12en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT           2
+/* rule13en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT           3
+/* rule14en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT               4
+/* rule15en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT               5
+/* rule16en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT               6
+/* rule17en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT               7
        u8 flags13;
+/* rule18en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT               0
+/* rule19en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK                0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT               1
+/* rule20en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT           2
+/* rule21en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT           3
+/* rule22en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT           4
+/* rule23en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT           5
+/* rule24en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT           6
+/* rule25en */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK            0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT           7
        u8 flags14;
+/* bit16 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK        0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT       0
+/* bit17 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK      0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT     1
+/* bit18 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK    0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT   2
+/* bit19 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK    0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT   3
+/* bit20 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK          0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT         4
+/* bit21 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK        0x1
 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT       5
+/* cf23 */
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK              0x3
 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT             6
        u8 edpm_event_id /* byte2 */;
@@ -1729,214 +2089,312 @@ struct xstormEthConnAgCtxDqExtLdPart {
        __le32 reg4 /* reg4 */;
 };

+
+
 struct xstorm_eth_hw_conn_ag_ctx {
        u8 reserved0 /* cdu_validation */;
        u8 eth_state /* state */;
        u8 flags0;
+/* exist_in_qm0 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
+/* exist_in_qm1 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT              1
+/* exist_in_qm2 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT              2
+/* exist_in_qm3 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
+/* bit4 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT              4
+/* cf_array_active */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT              5
+/* bit6 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT              6
+/* bit7 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT              7
        u8 flags1;
+/* bit8 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT              0
+/* bit9 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT              1
+/* bit10 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK               0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT              2
+/* bit11 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT                  3
+/* bit12 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT                  4
+/* bit13 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT                  5
+/* bit14 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
+/* bit15 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
        u8 flags2;
+/* timer0cf */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT                    0
+/* timer1cf */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT                    2
+/* timer2cf */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT                    4
+/* timer_stop_all */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT                    6
        u8 flags3;
+/* cf4 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT                    0
+/* cf5 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT                    2
+/* cf6 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT                    4
+/* cf7 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT                    6
        u8 flags4;
+/* cf8 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT                    0
+/* cf9 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK                     0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT                    2
+/* cf10 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK                    0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT                   4
+/* cf11 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK                    0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT                   6
        u8 flags5;
+/* cf12 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK                    0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT                   0
+/* cf13 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK                    0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT                   2
+/* cf14 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK                    0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT                   4
+/* cf15 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK                    0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT                   6
        u8 flags6;
+/* cf16 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
+/* cf_array_cf */
 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
+/* cf18 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK                   0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT                  4
+/* cf19 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
        u8 flags7;
+/* cf20 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK                0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
+/* cf21 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK              0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT             2
+/* cf22 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK               0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT              4
+/* cf0en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT                  6
+/* cf1en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT                  7
        u8 flags8;
+/* cf2en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT                  0
+/* cf3en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT                  1
+/* cf4en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT                  2
+/* cf5en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT                  3
+/* cf6en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT                  4
+/* cf7en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT                  5
+/* cf8en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT                  6
+/* cf9en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK                   0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT                  7
        u8 flags9;
+/* cf10en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK                  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT                 0
+/* cf11en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK                  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT                 1
+/* cf12en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK                  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT                 2
+/* cf13en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK                  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT                 3
+/* cf14en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK                  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT                 4
+/* cf15en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK                  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT                 5
+/* cf16en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
+/* cf_array_cf_en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
        u8 flags10;
+/* cf18en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
+/* cf19en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
+/* cf20en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
+/* cf21en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK              0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT             3
+/* cf22en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
+/* cf23en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
+/* rule0en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK              0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT             6
+/* rule1en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK              0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT             7
        u8 flags11;
+/* rule2en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK              0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT             0
+/* rule3en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK              0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT             1
+/* rule4en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
+/* rule5en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK                 0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT                3
+/* rule6en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK                 0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT                4
+/* rule7en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK                 0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT                5
+/* rule8en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
+/* rule9en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK                 0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT                7
        u8 flags12;
+/* rule10en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT               0
+/* rule11en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT               1
+/* rule12en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
+/* rule13en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
+/* rule14en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT               4
+/* rule15en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT               5
+/* rule16en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT               6
+/* rule17en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT               7
        u8 flags13;
+/* rule18en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT               0
+/* rule19en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK                0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT               1
+/* rule20en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
+/* rule21en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
+/* rule22en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
+/* rule23en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
+/* rule24en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
+/* rule25en */
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
        u8 flags14;
+/* bit16 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
+/* bit17 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
+/* bit18 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
+/* bit19 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
+/* bit20 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
+/* bit21 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
+/* cf23 */
 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK              0x3
 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
        u8 edpm_event_id /* byte2 */;
@@ -1949,4 +2407,5 @@ struct xstorm_eth_hw_conn_ag_ctx {
        __le16 conn_dpi /* conn_dpi */;
 };

+
 #endif /* __ECORE_HSI_ETH__ */
diff --git a/drivers/net/qede/base/ecore_hw_defs.h 
b/drivers/net/qede/base/ecore_hw_defs.h
index deb8e34..4456af4 100644
--- a/drivers/net/qede/base/ecore_hw_defs.h
+++ b/drivers/net/qede/base/ecore_hw_defs.h
@@ -10,19 +10,30 @@
 #define _ECORE_IGU_DEF_H_

 /* Fields of IGU PF CONFIGRATION REGISTER */
-#define IGU_PF_CONF_FUNC_EN       (0x1 << 0)   /* function enable        */
-#define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)   /* MSI/MSIX enable        */
-#define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)   /* INT enable             */
-#define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)   /* attention enable       */
-#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)   /* single ISR mode enable */
-#define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)   /* simd all ones mode     */
+/* function enable        */
+#define IGU_PF_CONF_FUNC_EN       (0x1 << 0)
+/* MSI/MSIX enable        */
+#define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)
+/* INT enable             */
+#define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)
+/* attention enable       */
+#define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)
+/* single ISR mode enable */
+#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)
+/* simd all ones mode     */
+#define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)

 /* Fields of IGU VF CONFIGRATION REGISTER */
-#define IGU_VF_CONF_FUNC_EN        (0x1 << 0)  /* function enable        */
-#define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)  /* MSI/MSIX enable        */
-#define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)  /* single ISR mode enable */
-#define IGU_VF_CONF_PARENT_MASK    (0xF)       /* Parent PF              */
-#define IGU_VF_CONF_PARENT_SHIFT   5   /* Parent PF              */
+/* function enable        */
+#define IGU_VF_CONF_FUNC_EN        (0x1 << 0)
+/* MSI/MSIX enable        */
+#define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)
+/* single ISR mode enable */
+#define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)
+/* Parent PF              */
+#define IGU_VF_CONF_PARENT_MASK    (0xF)
+/* Parent PF              */
+#define IGU_VF_CONF_PARENT_SHIFT   5

 /* Igu control commands
  */
diff --git a/drivers/net/qede/base/ecore_init_ops.h 
b/drivers/net/qede/base/ecore_init_ops.h
index f6b0a2d..d58c7d6 100644
--- a/drivers/net/qede/base/ecore_init_ops.h
+++ b/drivers/net/qede/base/ecore_init_ops.h
@@ -32,7 +32,9 @@ void ecore_init_iro_array(struct ecore_dev *p_dev);
  */
 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
                                    struct ecore_ptt *p_ptt,
-                                   int phase, int phase_id, int modes);
+                                   int               phase,
+                                   int               phase_id,
+                                   int               modes);

 /**
  * @brief ecore_init_hwfn_allocate - Allocate RT array, Store 'values' ptrs.
@@ -52,6 +54,7 @@ enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn 
*p_hwfn);
  */
 void ecore_init_free(struct ecore_hwfn *p_hwfn);

+
 /**
  * @brief ecore_init_clear_rt_data - Clears the runtime init array.
  *
@@ -96,6 +99,7 @@ void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
 #define STORE_RT_REG_AGG(hwfn, offset, val)                    \
        ecore_init_store_rt_agg(hwfn, offset, (u32 *)&val, sizeof(val))

+
 /**
  * @brief
  *      Initialize GTT global windows and set admin window
diff --git a/drivers/net/qede/base/ecore_mcp.h 
b/drivers/net/qede/base/ecore_mcp.h
index 8a2c84c..64c639f 100644
--- a/drivers/net/qede/base/ecore_mcp.h
+++ b/drivers/net/qede/base/ecore_mcp.h
@@ -30,19 +30,30 @@
                                  ecore_device_num_engines((_p_hwfn)->p_dev)))

 struct ecore_mcp_info {
-       osal_spinlock_t lock;   /* Spinlock used for accessing MCP mailbox */
+       /* Spinlock used for protecting the access to the MFW mailbox */
+       osal_spinlock_t lock;
        /* Flag to indicate whether sending a MFW mailbox is forbidden */
        bool block_mb_sending;
-       u32 public_base;        /* Address of the MCP public area */
-       u32 drv_mb_addr;        /* Address of the driver mailbox */
-       u32 mfw_mb_addr;        /* Address of the MFW mailbox */
-       u32 port_addr;          /* Address of the port configuration (link) */
-       u16 drv_mb_seq;         /* Current driver mailbox sequence */
-       u16 drv_pulse_seq;      /* Current driver pulse sequence */
-       struct ecore_mcp_link_params link_input;
-       struct ecore_mcp_link_state link_output;
+
+       /* Address of the MCP public area */
+       u32 public_base;
+       /* Address of the driver mailbox */
+       u32 drv_mb_addr;
+       /* Address of the MFW mailbox */
+       u32 mfw_mb_addr;
+       /* Address of the port configuration (link) */
+       u32 port_addr;
+
+       /* Current driver mailbox sequence */
+       u16 drv_mb_seq;
+       /* Current driver pulse sequence */
+       u16 drv_pulse_seq;
+
+       struct ecore_mcp_link_params       link_input;
+       struct ecore_mcp_link_state        link_output;
        struct ecore_mcp_link_capabilities link_capabilities;
-       struct ecore_mcp_function_info func_info;
+
+       struct ecore_mcp_function_info     func_info;

        u8 *mfw_mb_cur;
        u8 *mfw_mb_shadow;
diff --git a/drivers/net/qede/base/ecore_sp_api.h 
b/drivers/net/qede/base/ecore_sp_api.h
index 71e2359..a4cb507 100644
--- a/drivers/net/qede/base/ecore_sp_api.h
+++ b/drivers/net/qede/base/ecore_sp_api.h
@@ -23,10 +23,13 @@ struct eth_slow_path_rx_cqe;

 struct ecore_spq_comp_cb {
        void    (*function)(struct ecore_hwfn *,
-                        void *, union event_ring_data *, u8 fw_return_code);
+                        void *,
+                        union event_ring_data *,
+                        u8 fw_return_code);
        void    *cookie;
 };

+
 /**
  * @brief ecore_eth_cqe_completion - handles the completion of a
  *        ramrod on the cqe ring
diff --git a/drivers/net/qede/base/eth_common.h 
b/drivers/net/qede/base/eth_common.h
index 137b374..3213070 100644
--- a/drivers/net/qede/base/eth_common.h
+++ b/drivers/net/qede/base/eth_common.h
@@ -90,12 +90,17 @@
 #define ETH_RSS_KEY_SIZE_REGS               10
 /* number of available RSS engines in K2 */
 #define ETH_RSS_ENGINE_NUM_K2               207
+/* number of available RSS engines in BB */
 #define ETH_RSS_ENGINE_NUM_BB               127

 /* TPA constants */
+/* Maximum number of open TPA aggregations */
 #define ETH_TPA_MAX_AGGS_NUM              64
+/* Maximum number of additional buffers, reported by TPA-start CQE */
 #define ETH_TPA_CQE_START_LEN_LIST_SIZE   ETH_RX_MAX_BUFF_PER_PKT
+/* Maximum number of buffers, reported by TPA-continue CQE */
 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE    6
+/* Maximum number of buffers, reported by TPA-end CQE */
 #define ETH_TPA_CQE_END_LEN_LIST_SIZE     4

 /* Control frame check constants */
@@ -115,6 +120,7 @@ enum dest_port_mode {
        MAX_DEST_PORT_MODE
 };

+
 /*
  * Ethernet address type
  */
@@ -126,22 +132,31 @@ enum eth_addr_type {
        MAX_ETH_ADDR_TYPE
 };

+
 struct eth_tx_1st_bd_flags {
        u8 bitfields;
+/* Set to 1 in the first BD. (for debug) */
 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK         0x1
 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT        0
+/* Do not allow additional VLAN manipulations on this packet. */
 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK  0x1
 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
+/* IP checksum recalculation in needed */
 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK          0x1
 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT         2
+/* TCP/UDP checksum recalculation in needed */
 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK          0x1
 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT         3
+/* If set, need to add the VLAN in vlan field to the packet. */
 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK   0x1
 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT  4
+/* If set, this is an LSO packet. */
 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK              0x1
 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT             5
+/* Recalculate Tunnel IP Checksum (if Tunnel IP Header is IPv4) */
 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK     0x1
 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT    6
+/* Recalculate Tunnel UDP/GRE Checksum (Depending on Tunnel Type) */
 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK     0x1
 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT    7
 };
@@ -171,29 +186,50 @@ struct eth_tx_data_1st_bd {
  * The parsing information data for the second tx bd of a given packet.
  */
 struct eth_tx_data_2nd_bd {
+/* For tunnel with IPv6+ext - Tunnel header IP datagram length (in BYTEs) */
        __le16 tunn_ip_size;
        __le16 bitfields1;
+/* For Tunnel header with IPv6 ext. - Inner L2 Header Size (in 2-byte WORDs) */
 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK  0xF
 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
+/* For Tunnel header with IPv6 ext. - Inner L2 Header MAC DA Type
+ * (use enum eth_addr_type)
+ */
 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK       0x3
 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT      4
+/* Destination port mode. (use enum dest_port_mode) */
 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK            0x3
 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT           6
+/* Should be 0 in all the BDs, except the first one. (for debug) */
 #define ETH_TX_DATA_2ND_BD_START_BD_MASK                  0x1
 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT                 8
+/* For Tunnel header with IPv6 ext. - Tunnel Type (use enum eth_tx_tunn_type) 
*/
 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK                 0x3
 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT                9
+/* For LSO / Tunnel header with IPv6+ext - Set if inner header is IPv6 */
 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK           0x1
 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT          11
+/* For LSO / Tunnel header with IPv6+ext - Set if outer header has IPv6+ext */
 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK                  0x1
 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT                 12
+/* Set if Tunnel header has IPv6 ext. (3rd BD is required) */
 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK             0x1
 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT            13
+/* Set if (inner) L4 protocol is UDP. (Required when IPv6+ext (or tunnel with
+ * inner or outer Ipv6+ext) and l4_csum is set)
+ */
 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK                    0x1
 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT                   14
+/* The pseudo header checksum type in the L4 checksum field. Required when
+ * IPv6+ext and l4_csum is set. (use enum eth_l4_pseudo_checksum_mode)
+ */
 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK       0x1
 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT      15
        __le16 bitfields2;
+/* For inner/outer header IPv6+ext - (inner) L4 header offset (in 2-byte 
WORDs).
+ * For regular packet - offset from the beginning of the packet. For tunneled
+ * packet - offset from the beginning of the inner header
+ */
 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK     0x1FFF
 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT    0
 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK                 0x7
@@ -211,6 +247,7 @@ struct eth_edpm_fw_data {
        __le32 reserved;
 };

+
 /*
  * FW debug.
  */
@@ -268,8 +305,10 @@ struct eth_pmd_flow_flags {
 struct eth_fast_path_rx_reg_cqe {
        u8 type /* CQE type */;
        u8 bitfields;
+/* Type of calculated RSS hash (use enum rss_hash_type) */
 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK  0x7
 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
+/* Traffic Class */
 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK             0xF
 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT            3
 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK      0x1
@@ -290,14 +329,15 @@ struct eth_fast_path_rx_reg_cqe {
        struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
 };

+
 /*
  * TPA-continue ETH Rx FP CQE.
  */
 struct eth_fast_path_rx_tpa_cont_cqe {
        u8 type /* CQE type */;
        u8 tpa_agg_index /* TPA aggregation index */;
-       __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]
-           /* List of the segment sizes */;
+/* List of the segment sizes */
+       __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
        u8 reserved;
        u8 reserved1 /* FW reserved. */;
        __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* FW reserved. */;
@@ -305,6 +345,7 @@ struct eth_fast_path_rx_tpa_cont_cqe {
        struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
 };

+
 /*
  * TPA-end ETH Rx FP CQE .
  */
@@ -313,33 +354,36 @@ struct eth_fast_path_rx_tpa_end_cqe {
        u8 tpa_agg_index /* TPA aggregation index */;
        __le16 total_packet_len /* Total aggregated packet length */;
        u8 num_of_bds /* Total number of BDs comprising the packet */;
-       u8 end_reason /* Aggregation end reason. Use enum eth_tpa_end_reason */
-         ;
+/* Aggregation end reason. Use enum eth_tpa_end_reason */
+       u8 end_reason;
        __le16 num_of_coalesced_segs /* Number of coalesced TCP segments */;
        __le32 ts_delta /* TCP timestamp delta */;
-       __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]
-           /* List of the segment sizes */;
+/* List of the segment sizes */
+       __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
        __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* FW reserved. */;
        __le16 reserved1;
        u8 reserved2 /* FW reserved. */;
        struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
 };

+
 /*
  * TPA-start ETH Rx FP CQE.
  */
 struct eth_fast_path_rx_tpa_start_cqe {
        u8 type /* CQE type */;
        u8 bitfields;
+/* Type of calculated RSS hash (use enum rss_hash_type) */
 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK  0x7
 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
+/* Traffic Class */
 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK             0xF
 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT            3
 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK      0x1
 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT     7
        __le16 seg_len /* Segment length (packetLen from the parser) */;
-       struct parsing_and_err_flags pars_flags
-           /* Parsing and error flags from the parser */;
+/* Parsing and error flags from the parser */
+       struct parsing_and_err_flags pars_flags;
        __le16 vlan_tag /* 802.1q VLAN tag */;
        __le32 rss_hash /* RSS hash result */;
        __le16 len_on_first_bd /* Number of bytes placed on first BD */;
@@ -348,32 +392,34 @@ struct eth_fast_path_rx_tpa_start_cqe {
        struct eth_tunnel_parsing_flags tunnel_pars_flags;
        u8 tpa_agg_index /* TPA aggregation index */;
        u8 header_len /* Packet L2+L3+L4 header length */;
-       __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]
-           /* Additional BDs length list. */;
+/* Additional BDs length list. */
+       __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
        struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
        u8 reserved;
        struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
 };

+
 /*
  * The L4 pseudo checksum mode for Ethernet
  */
 enum eth_l4_pseudo_checksum_mode {
-       ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH
-               /* Pseudo Header checksum on packet is calculated
-                * with the correct packet length field.
-               */
-          ,
-       ETH_L4_PSEUDO_CSUM_ZERO_LENGTH
-           /* Pseudo Hdr checksum on packet is calc with zero len field. */
-          ,
+/* Pseudo Header checksum on packet is calculated with the correct packet 
length
+ * field.
+ */
+       ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
+/* Pseudo Header checksum on packet is calculated with zero length field. */
+       ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
        MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
 };

+
+
 struct eth_rx_bd {
        struct regpair addr /* single continues buffer */;
 };

+
 /*
  * regular ETH Rx SP CQE
  */
@@ -391,16 +437,18 @@ struct eth_slow_path_rx_cqe {
  * union for all ETH Rx CQE types
  */
 union eth_rx_cqe {
-       struct eth_fast_path_rx_reg_cqe fast_path_regular /* Regular FP CQE */;
-       struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start
-           /* TPA-start CQE */;
-       struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont
-           /* TPA-continue CQE */;
-       struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end /* TPA-end CQE */
-         ;
+/* Regular FP CQE */
+       struct eth_fast_path_rx_reg_cqe fast_path_regular;
+/* TPA-start CQE */
+       struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
+/* TPA-continue CQE */
+       struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
+/* TPA-end CQE */
+       struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
        struct eth_slow_path_rx_cqe slow_path /* SP CQE */;
 };

+
 /*
  * ETH Rx CQE type
  */
@@ -414,6 +462,7 @@ enum eth_rx_cqe_type {
        MAX_ETH_RX_CQE_TYPE
 };

+
 /*
  * Wrapper for PD RX CQE - used in order to cover full cache line when writing
  * CQE
@@ -423,6 +472,7 @@ struct eth_rx_pmd_cqe {
        u8 reserved[ETH_RX_CQE_GAP];
 };

+
 /*
  * Eth RX Tunnel Type
  */
@@ -434,19 +484,32 @@ enum eth_rx_tunn_type {
        MAX_ETH_RX_TUNN_TYPE
 };

+
+
 /*
  * Aggregation end reason.
  */
 enum eth_tpa_end_reason {
        ETH_AGG_END_UNUSED,
        ETH_AGG_END_SP_UPDATE /* SP configuration update */,
-       ETH_AGG_END_MAX_LEN
-           /* Maximum aggregation length or maximum buffer number used. */,
-       ETH_AGG_END_LAST_SEG
-           /* TCP PSH flag or TCP payload length below continue threshold. */,
+/* Maximum aggregation length or maximum buffer number used. */
+       ETH_AGG_END_MAX_LEN,
+/* TCP PSH flag or TCP payload length below continue threshold. */
+       ETH_AGG_END_LAST_SEG,
        ETH_AGG_END_TIMEOUT /* Timeout expiration. */,
+/* Packet header not consistency: different IPv4 TOS, TTL or flags, IPv6 TC,
+ * Hop limit or Flow label, TCP header length or TS options. In GRO different
+ * TS value, SMAC, DMAC, ackNum, windowSize or VLAN
+ */
        ETH_AGG_END_NOT_CONSISTENT,
+/* Out of order or retransmission packet: sequence, ack or timestamp not
+ * consistent with previous segment.
+ */
        ETH_AGG_END_OUT_OF_ORDER,
+/* Next segment cant be aggregated due to LLC/SNAP, IP error, IP fragment, IPv4
+ * options, IPv6 extension, IP ECN = CE, TCP errors, TCP options, zero TCP
+ * payload length , TCP flags or not supported tunnel header options.
+ */
        ETH_AGG_END_NON_TPA_SEG,
        MAX_ETH_TPA_END_REASON
 };
@@ -462,6 +525,8 @@ struct eth_tx_1st_bd {
        struct eth_tx_data_1st_bd data /* Parsing information data. */;
 };

+
+
 /*
  * The second tx bd of a given packet
  */
@@ -471,21 +536,29 @@ struct eth_tx_2nd_bd {
        struct eth_tx_data_2nd_bd data /* Parsing information data. */;
 };

+
 /*
  * The parsing information data for the third tx bd of a given packet.
  */
 struct eth_tx_data_3rd_bd {
        __le16 lso_mss /* For LSO packet - the MSS in bytes. */;
        __le16 bitfields;
+/* For LSO with inner/outer IPv6+ext - TCP header length (in 4-byte WORDs) */
 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK  0xF
 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
+/* LSO - number of BDs which contain headers. value should be in range
+ * (1..ETH_TX_MAX_LSO_HDR_NBD).
+ */
 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK         0xF
 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT        4
+/* Should be 0 in all the BDs, except the first one. (for debug) */
 #define ETH_TX_DATA_3RD_BD_START_BD_MASK        0x1
 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT       8
 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK       0x7F
 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT      9
+/* For tunnel with IPv6+ext - Pointer to tunnel L4 Header (in 2-byte WORDs) */
        u8 tunn_l4_hdr_start_offset_w;
+/* For tunnel with IPv6+ext - Total size of Tunnel Header (in 2-byte WORDs) */
        u8 tunn_hdr_size_w;
 };

@@ -498,6 +571,7 @@ struct eth_tx_3rd_bd {
        struct eth_tx_data_3rd_bd data /* Parsing information data. */;
 };

+
 /*
  * Complementary information for the regular tx bd of a given packet.
  */
@@ -506,6 +580,7 @@ struct eth_tx_data_bd {
        __le16 bitfields;
 #define ETH_TX_DATA_BD_RESERVED1_MASK  0xFF
 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
+/* Should be 0 in all the BDs, except the first one. (for debug) */
 #define ETH_TX_DATA_BD_START_BD_MASK   0x1
 #define ETH_TX_DATA_BD_START_BD_SHIFT  8
 #define ETH_TX_DATA_BD_RESERVED2_MASK  0x7F
@@ -522,14 +597,20 @@ struct eth_tx_bd {
        struct eth_tx_data_bd data /* Complementary information. */;
 };

+
 union eth_tx_bd_types {
        struct eth_tx_1st_bd first_bd /* The first tx bd of a given packet */;
-       struct eth_tx_2nd_bd second_bd /* The second tx bd of a given packet */
-         ;
+/* The second tx bd of a given packet */
+       struct eth_tx_2nd_bd second_bd;
        struct eth_tx_3rd_bd third_bd /* The third tx bd of a given packet */;
        struct eth_tx_bd reg_bd /* The common non-special bd */;
 };

+
+
+
+
+
 /*
  * Eth Tx Tunnel Type
  */
@@ -546,26 +627,31 @@ enum eth_tx_tunn_type {
  * Ystorm Queue Zone
  */
 struct xstorm_eth_queue_zone {
-       struct coalescing_timeset int_coalescing_timeset
-           /* Tx interrupt coalescing TimeSet */;
+/* Tx interrupt coalescing TimeSet */
+       struct coalescing_timeset int_coalescing_timeset;
        u8 reserved[7];
 };

+
 /*
  * ETH doorbell data
  */
 struct eth_db_data {
        u8 params;
+/* destination of doorbell (use enum db_dest) */
 #define ETH_DB_DATA_DEST_MASK         0x3
 #define ETH_DB_DATA_DEST_SHIFT        0
+/* aggregative command to CM (use enum db_agg_cmd_sel) */
 #define ETH_DB_DATA_AGG_CMD_MASK      0x3
 #define ETH_DB_DATA_AGG_CMD_SHIFT     2
-#define ETH_DB_DATA_BYPASS_EN_MASK    0x1
+#define ETH_DB_DATA_BYPASS_EN_MASK    0x1 /* enable QM bypass */
 #define ETH_DB_DATA_BYPASS_EN_SHIFT   4
 #define ETH_DB_DATA_RESERVED_MASK     0x1
 #define ETH_DB_DATA_RESERVED_SHIFT    5
+/* aggregative value selection */
 #define ETH_DB_DATA_AGG_VAL_SEL_MASK  0x3
 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
+/* bit for every DQ counter flags in CM context that DQ can increment */
        u8 agg_flags;
        __le16 bd_prod;
 };
diff --git a/drivers/net/qede/base/mcp_public.h 
b/drivers/net/qede/base/mcp_public.h
index d430752..96efc3c 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -252,11 +252,9 @@ struct lldp_config_params_s {
 struct lldp_status_params_s {
        u32 prefix_seq_num;
        u32 status; /* TBD */
-       /* Holds remote Chassis ID TLV header, subtype and 9B of payload.
-        */
+       /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
        u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
-       /* Holds remote Port ID TLV header, subtype and 9B of payload.
-        */
+       /* Holds remote Port ID TLV header, subtype and 9B of payload. */
        u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
        u32 suffix_seq_num;
 };
@@ -327,6 +325,7 @@ struct dcbx_app_priority_entry {
 #define DCBX_APP_PROTOCOL_ID_SHIFT  16
 };

+
 /* FW structure in BE */
 struct dcbx_app_priority_feature {
        u32 flags;
@@ -337,9 +336,9 @@ struct dcbx_app_priority_feature {
 #define DCBX_APP_ERROR_MASK             0x00000004
 #define DCBX_APP_ERROR_SHIFT            2
        /* Not in use
-        * #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
-        * #define DCBX_APP_DEFAULT_PRI_SHIFT      8
-        */
+       #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
+       #define DCBX_APP_DEFAULT_PRI_SHIFT      8
+       */
 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
 #define DCBX_APP_MAX_TCS_SHIFT          12
 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
@@ -398,13 +397,13 @@ struct dcbx_mib {
        u32 prefix_seq_num;
        u32 flags;
        /*
-        * #define DCBX_CONFIG_VERSION_MASK            0x00000007
-        * #define DCBX_CONFIG_VERSION_SHIFT           0
-        * #define DCBX_CONFIG_VERSION_DISABLED        0
-        * #define DCBX_CONFIG_VERSION_IEEE            1
-        * #define DCBX_CONFIG_VERSION_CEE             2
-        * #define DCBX_CONFIG_VERSION_STATIC          4
-        */
+       #define DCBX_CONFIG_VERSION_MASK            0x00000007
+       #define DCBX_CONFIG_VERSION_SHIFT           0
+       #define DCBX_CONFIG_VERSION_DISABLED        0
+       #define DCBX_CONFIG_VERSION_IEEE            1
+       #define DCBX_CONFIG_VERSION_CEE             2
+       #define DCBX_CONFIG_VERSION_STATIC          4
+       */
        struct dcbx_features features;
        u32 suffix_seq_num;
 };
@@ -439,6 +438,7 @@ struct public_global {
        u32 debug_mb_offset;
        u32 phymod_dbg_mb_offset;
        struct couple_mode_teaming cmt;
+/* Temperature in Celcius (-255C / +255C), measured every second. */
        s32 internal_temperature;
        u32 mfw_ver;
        u32 running_bundle_id;
@@ -732,7 +732,8 @@ struct public_func {

        /* MTU size per funciton is needed for the OV feature */
        u32 mtu_size;
-       /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
+/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
+
        /* For PCP values 0-3 use the map lower */
        /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
         * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
@@ -757,6 +758,7 @@ struct public_func {
 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001

+
 #define FUNC_MF_CFG_PROTOCOL_MASK               0x000000f0
 #define FUNC_MF_CFG_PROTOCOL_SHIFT              4
 #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000000
@@ -1040,49 +1042,105 @@ struct public_drv_mb {
 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
+/* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */
 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN                0x00010000
+/* Param should be set to the transaction size (up to 64 bytes) */
 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA         0x00020000
+/* MFW will place the file offset and len in file_att struct */
 #define DRV_MSG_CODE_NVM_GET_FILE_ATT          0x00030000
+/* Read 32bytes of nvram data. Param is [0:23] ? Offset [24:31] ?
+ * Len in Bytes
+ */
 #define DRV_MSG_CODE_NVM_READ_NVRAM            0x00050000
+/* Writes up to 32Bytes to nvram. Param is [0:23] ? Offset [24:31] ?
+ * Len in Bytes. In case this address is in the range of secured file in
+ * secured mode, the operation will fail
+ */
 #define DRV_MSG_CODE_NVM_WRITE_NVRAM           0x00060000
+/* Delete a file from nvram. Param is image_type. */
 #define DRV_MSG_CODE_NVM_DEL_FILE              0x00080000
+/* Reset MCP when no NVM operation is going on, and no drivers are loaded.
+ * In case operation succeed, MCP will not ack back.
+ */
 #define DRV_MSG_CODE_MCP_RESET                 0x00090000
+/* Temporary command to set secure mode, where the param is 0 (None secure) /
+ * 1 (Secure) / 2 (Full-Secure)
+ */
 #define DRV_MSG_CODE_SET_SECURE_MODE           0x000a0000
+/* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane,
+ * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port,
+ * [30:31] - port
+ */
 #define DRV_MSG_CODE_PHY_RAW_READ              0x000b0000
+/* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane,
+ * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port,
+ * [30:31] - port
+ */
 #define DRV_MSG_CODE_PHY_RAW_WRITE             0x000c0000
+/* Param: [0:15] - Address, [30:31] - port */
 #define DRV_MSG_CODE_PHY_CORE_READ             0x000d0000
+/* Param: [0:15] - Address, [30:31] - port */
 #define DRV_MSG_CODE_PHY_CORE_WRITE            0x000e0000
+/* Param: [0:3] - version, [4:15] - name (null terminated) */
 #define DRV_MSG_CODE_SET_VERSION               0x000f0000
+/* Halts the MCP. To resume MCP, user will need to use
+ * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers.
+ */
 #define DRV_MSG_CODE_MCP_HALT                  0x00100000
+/* Host shall provide buffer and size for MFW  */
 #define DRV_MSG_CODE_PMD_DIAG_DUMP             0x00140000
+/* Host shall provide buffer and size for MFW  */
 #define DRV_MSG_CODE_PMD_DIAG_EYE              0x00150000
+/* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address,
+ * [16:31] - offset
+ */
 #define DRV_MSG_CODE_TRANSCEIVER_READ          0x00160000
+/* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address,
+ * [16:31] - offset
+ */
 #define DRV_MSG_CODE_TRANSCEIVER_WRITE         0x00170000

+/* Set virtual mac address, params [31:6] - reserved, [5:4] - type,
+ * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN
+ */
 #define DRV_MSG_CODE_SET_VMAC                   0x00110000
+/* Set virtual mac address, params [31:6] - reserved, [5:4] - type,
+ * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN
+ */
 #define DRV_MSG_CODE_GET_VMAC                   0x00120000
 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3

+/* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */
 #define DRV_MSG_CODE_GET_STATS                  0x00130000
 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
 #define DRV_MSG_CODE_STATS_TYPE_RDMA           4

+/* indicate OCBB related information */
 #define DRV_MSG_CODE_OCBB_DATA                 0x00180000
+
+/* Set function BW, params[15:8] - min, params[7:0] - max */
 #define DRV_MSG_CODE_SET_BW                    0x00190000
 #define BW_MAX_MASK                            0x000000ff
 #define BW_MAX_SHIFT                           0
 #define BW_MIN_MASK                            0x0000ff00
 #define BW_MIN_SHIFT                           8
+
+/* When param is set to 1, all parities will be masked(disabled). When params
+ * are set to 0, parities will be unmasked again.
+ */
 #define DRV_MSG_CODE_MASK_PARITIES             0x001a0000
+/* param[0] - Simulate fan failure,  param[1] - simulate over temp. */
 #define DRV_MSG_CODE_INDUCE_FAILURE            0x001b0000
 #define DRV_MSG_FAN_FAILURE_TYPE               (1 << 0)
 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE       (1 << 1)

+/* Param: [0:15] - gpio number */
 #define DRV_MSG_CODE_GPIO_READ                 0x001c0000
+/* Param: [0:15] - gpio number, [16:31] - gpio value */
 #define DRV_MSG_CODE_GPIO_WRITE                        0x001d0000
 /* Param: [0:15] - gpio number */
 #define DRV_MSG_CODE_GPIO_INFO             0x00270000
@@ -1091,6 +1149,7 @@ struct public_drv_mb {
 #define DRV_MSG_CODE_BIST_TEST                 0x001e0000
 #define DRV_MSG_CODE_GET_TEMPERATURE            0x001f0000

+/* Set LED mode  params :0 operational, 1 LED turn ON, 2 LED turn OFF */
 #define DRV_MSG_CODE_SET_LED_MODE              0x00200000
 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] -
  * driver version (MAJ MIN BUILD SUB)
@@ -1244,9 +1303,12 @@ struct public_drv_mb {
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT              0
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK               0xF
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN            0x1
+/* Not Installed*/
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING            0x3
+/* installed but disabled by user/admin/OS */
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED   0x4
+/* installed and active */
 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE             0x5

 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT         0
@@ -1354,6 +1416,7 @@ struct public_drv_mb {
 #define FW_MSG_CODE_NVM_FILE_READ_ONLY         0x00200000
 #define FW_MSG_CODE_NVM_UNKNOWN_FILE           0x00300000
 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK     0x00400000
+/* MFW reject "mcp reset" command if one of the drivers is up */
 #define FW_MSG_CODE_MCP_RESET_REJECT           0x00600000
 #define FW_MSG_CODE_PHY_OK                     0x00110000
 #define FW_MSG_CODE_PHY_ERROR                  0x00120000
@@ -1389,6 +1452,7 @@ struct public_drv_mb {

 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff

+
        u32 fw_mb_param;
        /* Resource Allocation params - MFW  version support*/
 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK  0xFFFF0000
@@ -1420,7 +1484,10 @@ struct public_drv_mb {
 #define MCP_EVENT_MASK                          0xffff0000
 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000

+/* The union data is used by the driver to pass parameters to the scratchpad. 
*/
+
        union drv_union_data union_data;
+
 };

 /* MFW - DRV MB */
@@ -1477,7 +1544,9 @@ enum MFW_DRV_MSG_TYPE {

 struct public_mfw_mb {
        u32 sup_msgs;       /* Assigend with MFW_DRV_MSG_MAX */
+/* Incremented by the MFW */
        u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
+/* Incremented by the driver */
        u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
 };

-- 
1.8.3.1

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