From: Deepak Kumar JAIN <deepak.k.j...@intel.com>
enabled NULL crypto for Intel(R) QuickAssist Technology
Signed-off-by: Deepak Kumar Jain <deepak.k.jain at intel.com>
---
doc/guides/cryptodevs/qat.rst | 3 +-
doc/guides/rel_notes/release_16_11.rst | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++
drivers/crypto/qat/qat_crypto.c | 45 ++++++++++++++++++++++++
4 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 78a734f..bb62f22 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -49,6 +49,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR``
* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
+* ``RTE_CRYPTO_CIPHER_NULL``
Hash algorithms:
@@ -60,7 +61,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
-
+* ``RTE_CRYPTO_AUTH_NULL``
Limitations
-----------
diff --git a/doc/guides/rel_notes/release_16_11.rst
b/doc/guides/rel_notes/release_16_11.rst
index 9b2f102..9b2c775 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -42,6 +42,7 @@ New Features
* Added support for MD5_HMAC algorithm.
* Added support for SHA224-HMAC algorithm.
* Added support for SHA384-HMAC algorithm.
+ * Added support for NULL algorithm.
Resolved Issues
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index af8c176..d9437bc 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -720,6 +720,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
}
state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
break;
+ case ICP_QAT_HW_AUTH_ALGO_NULL:
+ break;
default:
PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
return -EFAULT;
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 60e2ba2..bc8d5b1 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -346,6 +346,47 @@ static const struct rte_cryptodev_capabilities
qat_pmd_capabilities[] = {
}, }
}, }
},
+ { /* NULL (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .aad_size = { 0 }
+ }, },
+ }, },
+ },
+ { /* NULL (CIPHER) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, },
+ }, }
+ },
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@@ -469,6 +510,8 @@ qat_crypto_sym_configure_session_cipher(struct
rte_cryptodev *dev,
session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
break;
case RTE_CRYPTO_CIPHER_NULL:
+ session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
+ break;
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_3DES_CBC:
case RTE_CRYPTO_CIPHER_AES_ECB:
@@ -600,6 +643,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev
*dev,
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
break;
case RTE_CRYPTO_AUTH_NULL:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
+ break;
case RTE_CRYPTO_AUTH_SHA1:
case RTE_CRYPTO_AUTH_SHA256:
case RTE_CRYPTO_AUTH_SHA512:
--
2.5.5
