Thanks!
Yongseok
> On Sep 13, 2017, at 10:23 PM, Shahaf Shuler <shah...@mellanox.com> wrote:
>
> Hi Yongseok,
>
> Wednesday, September 13, 2017 10:52 PM, Yongseok Koh:
>>>
>>> +/* Maximum number of DS in WQE. */
>>> +#define MLX5_MAX_DS 63
>> How about make it consistent with MLX5_MPW_DSEG_MAX by naming
>> MLX5_DSEG_MAX?
>
> It doesn't have the same meaning.
>
> The MLX5_MPW_DSEG_MAX is to limit the number of mbuf segments (buf->nb_segs)
> for multi packet wqe. The inline part is taken into account differently.
> The MLX_MAX_DS is to limit the number data segments (i.e.
> MLX5_WQE_DWORD_SIZE) that could be set into a WQE. This includes everything
> (inline, ctrl seg, eth seg, pointers).
> For the regular Tx burst there are many options for different inline sizes
> which impact on the max number of mbuf segments possible.
I should've been clearer. I just suggested a small change from DS to DSEG as I
thought DS and DSEG are same. But if it just comes from the field name in WQE
Ctrl segment, MLX5_WQE_DS_MAX or MLX5_WQE_CTRL_DS_MAX could be good. I hoped it
could be a little more explanatory. I'm not good at naming, will defer to you.
:-)
> BTW - am still not sure why we have the MLX5_MPW_DSEG_MAX limitation.
I don't know either. We should discuss it with chip design.
Thanks
Yongseok
