On 01/08/2018 04:34 PM, Stephen Hemminger wrote:
On Mon, 8 Jan 2018 14:51:27 +0100 Maxime Coquelin <[email protected]> wrote:Intel VT-d supports different address widths for the IOVAs, from 39 bits to 56 bits. While recent processors support at least 48 bits, VT-d emulation currently only supports 39 bits. It makes DMA mapping to fail in this case when using VA as IOVA mode, as user-space virtual addresses uses up to 47 bits (see kernel's Documentation/x86/x86_64/mm.txt). This patch parses VT-d CAP register value available in sysfs, and forbid VA as IOVA mode if the GAW is 39 bits or unknown. Fixes: f37dfab21c98 ("drivers/net: enable IOVA mode for Intel PMDs") Cc: [email protected] Signed-off-by: Maxime Coquelin <[email protected]> --- Hi, I'm not super happy with the patch as it does platform specific things in generic code, but there are no placeholder for IOMMU/VT-d at the moment. As this patch is to be backported to v17.11 LTS, it cannot be a big rework. If you have some suggestion to improve it, please let me know. The fix is quite urgent, as guest device assignment with vIOMMU is broken in mainline & v17.11 LTS. Advantage of this fix over forbidding VA as IOVA when running in emulation is that VT-d emulation will soon support 48 bits, so this is future proof. Also, VT-d spec supports 39 bits, so we could have physical CPUs supporting it, even if I don't know any. Thanks, MaximeYou are assumming that if IOMMU is present that it is being used (ie VFIO). What about the case of direct access to PF device via IGB_UIO?
As soon as one device is bound to UIO or VFIO in noiomu mode, PA as IOVA mode will be selected. This is done in rte_pci_get_iommu_class(), by calling pci_one_device_bound_uio() and rte_vfio_noiommu_is_enabled().
+static inline bool +pci_one_device_iommu_support_va(struct rte_pci_device *dev) +{This is not in fast path, there is no reason it should be inline
Ok, I will remove inlining in v2. I added it for consistency with the other functions declared above. Thanks, Maxime
