On 4/4/07, Mikhail Fursov <[EMAIL PROTECTED]> wrote:
On 4/4/07, Alexey Petrenko <[EMAIL PROTECTED]> wrote: > > 2007/4/4, Gregory Shimansky <[EMAIL PROTECTED]>: > > > > I would like to see these modifications. I wonder what you've done in > > port/src/thread/linux/apr_thread_ext.c and vmcore/include/atomics.h. > > They contain mfence and sfence instructions in inline assembly which > > have to be changed to something else on P3.
MemoryWriteBarrier() etc. should be no-ops on PIII. x86 is already strongly ordered for writes ?
> Can we produce separate binary build for P3 if it is not easy to > replace mfence/sfence? Jitrino can use runtime detection of CPU features supported and emit appropriate code. Can we do the same with VM (check flag) to avoid multiple distributions?
Jitrino generates code late, the VM doesn't. So I am not sure how this would work unless we link all versions of the asm's and then decide which ones to call at runtime, which has a cost. My suggestion would be that if we want the x86-32 bits to be PIII compatible, we should only use PIII instructions ( upto SSE ) in all the static 32 bit binaries. The jit can choose to generate more advanced instruction sequences at runtime based on cpuid if the paltform supports it.
-- Mikhail Fursov
