So the Jitrino isn't generating i586 (Pentium) instructions directly, it's generating P4 instructions and the optimizer is translating them down? Is that the design?
On 4/19/07, Mikhail Fursov <[EMAIL PROTECTED]> wrote:
On 4/19/07, Pavel Ozhdikhin <[EMAIL PROTECTED]> wrote: > > p5 - optimization pass for Jitrino.OPT JIT compiler which substitutes SSE > instructions with non-SSE (introduced in HARMONY-3246) > k5 - I think Mikhail meant p5 here. :) > > Yes I was confused by its name. Can we rename it sse2tox87 ? It what it really does. -- Mikhail Fursov
