Hi all.
I'm trying to run application (Digital Video Recording app) on console
depends on Kernel framebuffer overlay support.
but IEGD driver only support X11 overlay drivers.
Out Target bussiness platform must runs console environment, Because
it needs much cpu and response speed.
I used vidix(Video interface for *nix ) dirvers with ati video card.
like this i just want to use direct graphic acccess .
I attached sample drivers i made but it's not working, because i
cannot get overlay base address .
How to get overlay base address in kernel drivers .
maybe you can point me to the right direction.
Best Regards.
Steven.
############################################################################
#########
/*
* Intel video overlay driver for direct graphic access
One hardware overlay is implemented in the graphics device. Note that
most of the
Overlay registers are indirectly written by first setting up a buffer in
memory and then
instructing the graphics controller to update the on-chip registers from
this buffer.
Software can invoke the update process by either writing to the OVADD
(with
restructions) register or by issuing an Overlay Flip instruction
(MI_OVERLAY_FLIP).
The Overlay registers can be used for overlay gamma correction and color
adjustment.
They are read/written directly by MMIO(memory mapped I/O) without going
through
the buffer in memory.
* Address Range
* 30000h-3FFFFh Overlay Registers
* 05000h-05FFFh GMBUS and I/O Control
* 06000h-06FFFh Display Clocks and Clock Gating
* 0A000h-0AFFFh Display Palette A/B Registers
* 60000h-600FFh Display Pipeline A
* 61000h-610FFh Display Pipeline B
*
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/byteorder/swab.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/io.h>
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
extern int wait_ring(struct intelfb_info *dinfo, int n);
#include "i810_reg.h"
//#include "i830_reg.h"
//#include "i915_reg.h"
#include "intelfb.h"
#include "intelfbhw.h"
#include "intel_vid.h"
#include "intel_ioctl.h"
#include "fourcc.h"
#include "generic_math.h"
/*
* Overlay Registers(30000h-03ffffh)
_____________________
|_____________________|
| Graphics Controller |
| Registger Range |
| (512 KB) |
| ------------------- |
| Overlay 0 Reg |
base+301xxh | ------------------- |
| |
(Base = MMADR PCI Reg.) |_____________________|
| Graphics Memory |
| ------------------- |
| Overlay 0 Reg |
Base+xxh | ------------------- |
(Base = OV0ADD Reg. ) | |
|_____________________|
* 30000h-30003h OVADDR Overlay Register Update Address(RW)
* 30004h-30007h OTEST Overlay Test Register(RW)
* 30008h-3000Bh DOVSTA Display/Overlay Status
* 3000Ch-3000Fh DOVSTAEX Display/Overlay Extended Status
*/
/*
* Overlay Memory Offset Registers
* Register Mnemonic On-chip Address offset
*/
typedef struct {
uint32_t OBUF_0Y; /* 30100h-30103h Overlay Buffer 0 Y Pointer */
uint32_t OBUF_1Y; /* 30104h-30107h Overlay Buffer 1 Y Pointer*/
uint32_t OBUF_0U; /* 30108h-3010Bh Overlay Buffer 0 U Pointer*/
uint32_t OBUF_0V; /* 3010Ch-3010Fh Overlay Buffer 0 V Pointer*/
uint32_t OBUF_1U; /* 30110h-30113h Overlay Buffer 1 U Pointer*/
uint32_t OBUF_1V; /* 30114h??0117h Overlay Buffer 1 V Pointer */
uint32_t OSTRIDE; /* 30118h??011Bh Overlay Stride */
uint32_t YRGB_VPH; /* 3011Ch??011Fh Y/RGB Vertical Phase 0/1 */
uint32_t UV_VPH; /* 30120h??0123h UV Vertical Phase 0/1 */
uint32_t HORZ_PH; /* 30124h??0127h Horizontal Phase */
uint32_t INIT_PHS; /* 30128h??012Bh Initial Phase Shift */
uint32_t DWINPOS; /* 3012Ch-3012Fh Destination Window Position */
uint32_t DWINSZ; /* 30130h-30133h Destination Window Size */
uint32_t SWIDTH; /* 30134h-30137h Source Width */
uint32_t SWIDTHSW; /* 3013Ch??013Fh Source Height */
uint32_t SHEIGHT; /* 3013Ch-3013Fh Source Height */
uint32_t YRGBSCALE; /* 30140h-30143h Y/RGB Scale Factor */
uint32_t UVSCALE; /* 30144h-30147h U V Scale Factor */
uint32_t OCLRC0; /* 30148h??014Bh Overlay Color Correction 0 */
uint32_t OCLRC1; /* 3014Ch??014Fh Overlay Color Correction 1 */
uint32_t DCLRKV; /* 30150h-30153h Destination Color Key Value */
uint32_t DCLRKM; /* 30154h-30157h Destination Color Key Mask */
uint32_t SCLRKVH; /* 30158h??015Bh Source Chroma Key Value High */
uint32_t SCLRKVL; /* 3015Ch??015Fh Source Chroma Key Value Low */
uint32_t SCLRKEN; /* 30160h??0163h Source Chroma Key Enable */
uint32_t OCONFIG; /* 30164h-30167h Overlay Configuration */
uint32_t OCMD; /* 30168h-3016Bh Overlay Command */
uint32_t RESERVED1; /* 0x6C */
uint32_t OSTART_0Y; /* 30170h-30173h Overlay Surface Y 0 Base Address
for i965 */
uint32_t OSTART_1Y; /* 30174h-30177h Overlay Surface Y 1 Base Address
for i965 */
uint32_t OSTART_0U;
uint32_t OSTART_0V;
uint32_t OSTART_1U;
uint32_t OSTART_1V;
uint32_t OTILEOFF_0Y;
uint32_t OTILEOFF_1Y;
uint32_t OTILEOFF_0U;
uint32_t OTILEOFF_0V;
uint32_t OTILEOFF_1U;
uint32_t OTILEOFF_1V;
uint32_t FASTHSCALE; /* 0xA0 */
uint32_t UVSCALEV; /* 0xA4 */
uint32_t RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 -
0x1FC */
uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /*
0x500 */
uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
uint16_t RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; /*
30768h??07FFh */
} IntelOverlayRegRec, *IntelOverlayRegPtr;
/*
* Limiting the class to PCI_CLASS_DISPLAY_VGA prevents function 1 of the
* mobile chipsets from being registered.
*/
#if DETECT_VGA_CLASS_ONLY
#define INTELFB_CLASS_MASK ~0 << 8
#else
#define INTELFB_CLASS_MASK 0
#endif
static struct pci_device_id intelfb_pci_table[] __devinitdata = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_830M, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_830M },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_845G, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_845G },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_85XGM, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_85XGM },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_865G, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_865G },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915G, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915G },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915GM, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915GM },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945G, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945G },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945GM, PCI_ANY_ID,
PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945GM },
{ 0, }
};
static int accel = 1;
static int vram = 4;
static int hwcursor = 0;
static int mtrr = 1;
static int fixed = 0;
static int noinit = 0;
static int noregister = 0;
static int probeonly = 0;
static int idonly = 0;
static int bailearly = 0;
static int voffset = 48;
static char *mode = NULL;
IntelPortPrivRec g_Priv;
IntelOverlayRegRec g_overlay;
IntelRec g_IntelRec;
static struct intelfb_info *g_dinfo;
static void intel_overlay_on(struct intelfb_info *dinfo );
static void intel_overlay_off(struct intelfb_info *dinfo);
/***************************************************************
* mtrr support functions *
***************************************************************/
#ifdef CONFIG_MTRR
static inline void __devinit set_mtrr(struct intelfb_info *dinfo)
{
dinfo->mtrr_reg = mtrr_add(dinfo->aperture.physical,
dinfo->aperture.size, MTRR_TYPE_WRCOMB,
1);
if (dinfo->mtrr_reg < 0) {
ERR_MSG("unable to set MTRR\n");
return;
}
dinfo->has_mtrr = 1;
}
static inline void unset_mtrr(struct intelfb_info *dinfo)
{
if (dinfo->has_mtrr)
mtrr_del(dinfo->mtrr_reg, dinfo->aperture.physical,
dinfo->aperture.size);
}
#else
#define set_mtrr(x) WRN_MSG("MTRR is disabled in the kernel\n")
#define unset_mtrr(x) do { } while (0)
#endif /* CONFIG_MTRR */
static void intel_compare_overlay(struct intelfb_info *dinfo)
{
IntelOverlayRegPtr overlay;
int size = 0x100;
int i;
uint32_t val;
int bad = 0;
overlay = &g_overlay;
DBG_MSG("[%s]enter\n", __func__);
for (i = 0; i < size; i += 4) {
val = INREG(0x30100 + i);
DBG_MSG("0x%05x value (0x%lx)\n", 0x30100 + i, val);
#if 0
if (val != overlay[i / 4]) {
ERR_MSG("0x%05x value doesn't match (0x%lx !=
0x%lx)\n", 0x30100 + i, val, overlay[i / 4]);
bad++;
}
#endif
}
DBG_MSG("[%s]leave\n", __func__);
}
static void intel_overlay_on(struct intelfb_info *dinfo )
{
IntelOverlayRegPtr overlay;
uint8_t deactivate = FALSE;
overlay = &g_overlay;
DBG_MSG("[%s]enter %p\n", __func__, dinfo);
#if 0 //kscho, for temp
if (*pI830->overlayOn) return;
#endif
/*
* On I830, if pipe A is off when the overlayis enabled, it will
fail to
* turn on and blank the entire screen or lock up the ring. Light up
pipe
* A in this case to provide a clock for the overlay hardware
*/
overlay->OCMD &= ~OVERLAY_ENABLE;
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
START_RING(6);
DBG_MSG("[%s:%d]error\n", __func__, __LINE__);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
OUT_RING(MI_NOOP);
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_ON);
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
#if 0 //kscho, for temp
if (OVERLAY_NOPHYSICAL(dinfo))
OUT_RING(pI830->overlay_regs->offset | OFC_UPDATE);
else
OUT_RING(pI830->overlay_regs->bus_addr | OFC_UPDATE);
#endif
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
/* Wait for the overlay to light up before attempting to use it */
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
OUT_RING(MI_NOOP);
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
ADVANCE_RING();
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
#if 0 //kscho, for temp
i830WaitSync(pScrn);
/*
* If we turned pipe A on up above, turn it
* back off
*/
if (deactivate)
i830_pipe_a_require_deactivate (pScrn);
OVERLAY_DEBUG("overlay_on\n");
*pI830->overlayOn = TRUE;
#endif
DBG_MSG("[%s:%d]\n", __func__, __LINE__);
overlay->OCMD |= OVERLAY_ENABLE;
DBG_MSG("[%s]leave\n", __func__);
}
static void intel_overlay_continue(struct intelfb_info *dinfo, uint8_t
update_filter)
{
IntelOverlayRegPtr overlay;
uint32_t flip_addr;
overlay = &g_overlay;
printk("[%s]enter\n", __func__);
#if 0 //kscho, for temp
if (!*pI830->overlayOn)
return;
if (OVERLAY_NOPHYSICAL(dinfo))
flip_addr = pI830->overlay_regs->offset;
else
flip_addr = pI830->overlay_regs->bus_addr;
if (update_filter) flip_addr |= OFC_UPDATE;
OVERLAY_DEBUG ("overlay_continue cmd 0x%08" PRIx32 " -> 0x%08" PRIx32
" sta 0x%08" PRIx32 "\n",
overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
#endif
START_RING(4);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
OUT_RING(MI_NOOP);
OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
OUT_RING(flip_addr);
ADVANCE_RING();
printk("[%s]overlay_continue\n", __func__);
printk("[%s]leave\n", __func__);
}
static void intel_overlay_off(struct intelfb_info *dinfo)
{
IntelOverlayRegPtr overlay;
overlay = &g_overlay;
printk("[%s]enter\n", __func__);
#if 0 //kscho, for temp
if (!*pI830->overlayOn)
return;
#endif
/*
* Wait for overlay to go idle. This has to be
* separated from the turning off state by a WaitSync
* to ensure the overlay will not read OCMD early and
* disable the overlay before the commands here are
* executed
*/
{
START_RING(2);
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
OUT_RING(MI_NOOP);
ADVANCE_RING();
#if 0 //kscho for temp
i830WaitSync(pScrn);
#endif
}
/*
* Turn overlay off
*/
{
overlay->OCMD &= ~OVERLAY_ENABLE;
#if 0 //kscho for temp
OVERLAY_DEBUG ("overlay_off cmd 0x%08" PRIx32 " -> 0x%08"
PRIx32 " sta 0x%08" PRIx32 "\n",
overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
#endif
START_RING(6);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
OUT_RING(MI_NOOP);
OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
#if 0 //kscho for temp
if (OVERLAY_NOPHYSICAL(dinfo))
OUT_RING(pI830->overlay_regs->offset);
else
OUT_RING(pI830->overlay_regs->bus_addr);
#endif
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
OUT_RING(MI_NOOP);
ADVANCE_RING();
#if 0 //kscho for temp
i830WaitSync(pScrn);
#endif
}
#if 0 //kscho for temp
*pI830->overlayOn = FALSE;
#endif
printk("[%s]overlay_off\n", __func__);
printk("[%s]leave\n", __func__);
}
static void intel_reset_video()
{
IntelOverlayRegPtr overlay;
IntelPortPrivPtr pPriv;
pPriv = &g_Priv;
overlay = &g_overlay;
printk("[%s]enter\n", __func__);
/*
* Default to maximum image size in YV12
*/
memset(overlay, 0, sizeof(*overlay));
overlay->YRGB_VPH = 0;
overlay->UV_VPH = 0;
overlay->HORZ_PH = 0;
overlay->INIT_PHS = 0;
overlay->DWINPOS = 0;
overlay->DWINSZ = 0;
overlay->SWIDTH = 0;
overlay->SWIDTHSW = 0;
overlay->SHEIGHT = 0;
overlay->OCLRC0 = (pPriv->contrast << 18) | (pPriv->brightness &
0xff);
overlay->OCLRC1 = pPriv->saturation;
overlay->FASTHSCALE = 0;
#if 0 //kscho for temp
/*
* Enable destination color keying
*/
switch (pScrn->depth) {
case 8:
overlay->DCLRKV = 0;
overlay->DCLRKM = 0xffffff | DEST_KEY_ENABLE;
break;
case 15:
overlay->DCLRKV = RGB15ToColorKey(pPriv->colorKey);
overlay->DCLRKM = 0x070707 | DEST_KEY_ENABLE;
break;
case 16:
overlay->DCLRKV = RGB16ToColorKey(pPriv->colorKey);
overlay->DCLRKM = 0x070307 | DEST_KEY_ENABLE;
break;
default:
overlay->DCLRKV = pPriv->colorKey;
overlay->DCLRKM = DEST_KEY_ENABLE;
break;
}
#endif
overlay->SCLRKVH = 0;
overlay->SCLRKVL = 0;
overlay->SCLRKEN = 0; /* source color key disable */
overlay->OCONFIG = CC_OUT_8BIT;
/*
* Select which pipe the overlay is enabled on.
*/
#if 0 //kscho for temp
overlay->OCONFIG &= ~OVERLAY_PIPE_MASK;
if (i830_crtc_pipe (pPriv->current_crtc) == 0)
overlay->OCONFIG |= OVERLAY_PIPE_A;
else
overlay->OCONFIG |= OVERLAY_PIPE_B;
#endif
printk("[%s]leave\n", __func__);
}
static int
intel_swidth (struct intelfb_info *dinfo, unsigned int offset,
unsigned int width, unsigned int mask, int shift)
{
int swidth = ((offset + width + mask) >> shift) - (offset >> shift);
if (IS_I9XX(dinfo))
swidth <<= 1;
swidth -= 1;
return swidth << 2;
}
static void intel_display_video(struct intelfb_info *dinfo,
int id, short width, short height, int dstPitch,
int x1, int y1, int x2, int y2,
BoxPtr dstBox,
short src_w, short src_h, short drw_w, short drw_h )
{
unsigned int swidth, swidthy, swidthuv;
unsigned int mask, shift, offsety, offsetu;
int tmp;
uint32_t OCMD;
uint8_t scaleChanged = FALSE;
IntelOverlayRegPtr overlay;
IntelPortPrivPtr pPriv;
pPriv = &g_Priv;
overlay = &g_overlay;
printk("[%s]enter %p\n", __func__, dinfo);
if (pPriv->currentBuf == 0) {
offsety = pPriv->YBuf0offset;
offsetu = pPriv->UBuf0offset;
} else {
offsety = pPriv->YBuf1offset;
offsetu = pPriv->UBuf1offset;
}
switch (id) {
case FOURCC_YV12:
case FOURCC_I420:
overlay->SWIDTH = width | ((width/2 & 0x7ff) << 16);
swidthy = intel_swidth (dinfo, offsety, width, mask,
shift);
swidthuv = intel_swidth (dinfo, offsetu, width/2, mask,
shift);
overlay->SWIDTHSW = (swidthy) | (swidthuv << 16);
overlay->SHEIGHT = height | ((height / 2) << 16);
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
overlay->SWIDTH = width;
swidth = ((offsety + (width << 1) + mask) >> shift) -
(offsety >> shift);
if (IS_I9XX(dinfo)) swidth <<= 1;
swidth -= 1;
swidth <<= 2;
#if 1 //kscho
printk("[%s]swidthsw is old %d new %d\n", __func__,
swidth, intel_swidth (dinfo, offsety, width << 1,
mask, shift));
#endif
overlay->SWIDTHSW = swidth;
overlay->SHEIGHT = height;
break;
}
overlay->DWINPOS = (dstBox->y1 << 16) | dstBox->x1;
overlay->DWINSZ = (((dstBox->y2 - dstBox->y1) << 16) |
(dstBox->x2 - dstBox->x1));
printk("dstBox: x1: %d, y1: %d, x2: %d, y2: %d\n",
dstBox->x1, dstBox->y1, dstBox->x2, dstBox->y2);
/* buffer locations */
overlay->OBUF_0Y = pPriv->YBuf0offset;
overlay->OBUF_0U = pPriv->UBuf0offset;
overlay->OBUF_0V = pPriv->VBuf0offset;
if(pPriv->doubleBuffer) {
overlay->OBUF_1Y = pPriv->YBuf1offset;
overlay->OBUF_1U = pPriv->UBuf1offset;
overlay->OBUF_1V = pPriv->VBuf1offset;
}
//printk("pos: 0x%" PRIx32 ", size: 0x%" PRIx32 "\n", overlay-
>DWINPOS, overlay->DWINSZ);
printk("dst: %d x %d, src: %d x %d\n", drw_w, drw_h, src_w, src_h);
overlay->DWINPOS = (dstBox->y1 << 16) | dstBox->x1;
overlay->DWINSZ = (((dstBox->y2 - dstBox->y1) << 16) | (dstBox->x2 -
dstBox->x1));
printk("dstBox: x1: %d, y1: %d, x2: %d, y2: %d\n", dstBox->x1,
dstBox->y1, dstBox->x2, dstBox->y2);
/* buffer locations */
overlay->OBUF_0Y = pPriv->YBuf0offset;
overlay->OBUF_0U = pPriv->UBuf0offset;
overlay->OBUF_0V = pPriv->VBuf0offset;
if(pPriv->doubleBuffer) {
overlay->OBUF_1Y = pPriv->YBuf1offset;
overlay->OBUF_1U = pPriv->UBuf1offset;
overlay->OBUF_1V = pPriv->VBuf1offset;
}
//printk("pos: 0x%" PRIx32 ", size: 0x%" PRIx32 "\n", overlay-
>DWINPOS, overlay->DWINSZ);
printk("dst: %d x %d, src: %d x %d\n", drw_w, drw_h, src_w, src_h);
#if 0
/*
* Calculate horizontal and vertical scaling factors and polyphase
* coefficients.
*/
{
int xscaleInt, xscaleFract, yscaleInt, yscaleFract;
int xscaleIntUV, xscaleFractUV;
int yscaleIntUV, yscaleFractUV;
/* UV is half the size of Y -- YUV420 */
int uvratio = 2;
uint32_t newval;
coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES];
coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES];
int i, j, pos;
/*
* Y down-scale factor as a multiple of 4096.
*/
xscaleFract = ((src_w - 1) << 12) / drw_w;
yscaleFract = ((src_h - 1) << 12) / drw_h;
/* Calculate the UV scaling factor. */
xscaleFractUV = xscaleFract / uvratio;
yscaleFractUV = yscaleFract / uvratio;
/*
* To keep the relative Y and UV ratios exact, round the Y
scales
* to a multiple of the Y/UV ratio.
*/
xscaleFract = xscaleFractUV * uvratio;
yscaleFract = yscaleFractUV * uvratio;
/* Integer (un-multiplied) values. */
xscaleInt = xscaleFract >> 12;
yscaleInt = yscaleFract >> 12;
xscaleIntUV = xscaleFractUV >> 12;
yscaleIntUV = yscaleFractUV >> 12;
#if 0
OVERLAY_DEBUG("xscale: %x.%03x, yscale: %x.%03x\n",
xscaleInt,
xscaleFract & 0xFFF, yscaleInt, yscaleFract & 0xFFF);
OVERLAY_DEBUG("UV xscale: %x.%03x, UV yscale: %x.%03x\n",
xscaleIntUV,
xscaleFractUV & 0xFFF, yscaleIntUV, yscaleFractUV &
0xFFF);
#endif
/* shouldn't get here */
if (xscaleInt > 7) {
printk(KERN_ERR"[%s]xscale: bad scale\n", __func__);
return;
}
/* shouldn't get here */
if (xscaleIntUV > 7) {
printk(KERN_ERR"[%s]xscaleUV: bad scale\n",
__func__);
return;
}
newval = (xscaleInt << 16) |
((xscaleFract & 0xFFF) << 3) | ((yscaleFract & 0xFFF) <<
20);
if (newval != overlay->YRGBSCALE) {
scaleChanged = TRUE;
overlay->YRGBSCALE = newval;
}
newval = (xscaleIntUV << 16) | ((xscaleFractUV & 0xFFF) <<
3) |
((yscaleFractUV & 0xFFF) << 20);
if (newval != overlay->UVSCALE) {
scaleChanged = TRUE;
overlay->UVSCALE = newval;
}
newval = yscaleInt << 16 | yscaleIntUV;
if (newval != overlay->UVSCALEV) {
scaleChanged = TRUE;
overlay->UVSCALEV = newval;
}
#if 0
/* Recalculate coefficients if the scaling changed. */
/*
* Only Horizontal coefficients so far.
*/
if (scaleChanged) {
double fCutoffY;
double fCutoffUV;
fCutoffY = xscaleFract / 4096.0;
fCutoffUV = xscaleFractUV / 4096.0;
/* Limit to between 1.0 and 3.0. */
if (fCutoffY < MIN_CUTOFF_FREQ)
fCutoffY = MIN_CUTOFF_FREQ;
if (fCutoffY > MAX_CUTOFF_FREQ)
fCutoffY = MAX_CUTOFF_FREQ;
if (fCutoffUV < MIN_CUTOFF_FREQ)
fCutoffUV = MIN_CUTOFF_FREQ;
if (fCutoffUV > MAX_CUTOFF_FREQ)
fCutoffUV = MAX_CUTOFF_FREQ;
UpdateCoeff(N_HORIZ_Y_TAPS, fCutoffY, TRUE, TRUE,
xcoeffY);
UpdateCoeff(N_HORIZ_UV_TAPS, fCutoffUV, TRUE,
FALSE, xcoeffUV);
for (i = 0; i < N_PHASES; i++) {
for (j = 0; j < N_HORIZ_Y_TAPS; j++) {
pos = i * N_HORIZ_Y_TAPS + j;
overlay->Y_HCOEFS[pos] =
(xcoeffY[pos].sign << 15 |
xcoeffY[pos].exponent << 12 |
xcoeffY[pos].mantissa);
}
}
for (i = 0; i < N_PHASES; i++) {
for (j = 0; j < N_HORIZ_UV_TAPS; j++) {
pos = i * N_HORIZ_UV_TAPS + j;
overlay->UV_HCOEFS[pos] =
(xcoeffUV[pos].sign << 15 | xcoeffUV[pos].exponent << 12 |
xcoeffUV[pos].mantissa);
}
}
}
#endif
}
#endif
OCMD = OVERLAY_ENABLE;
switch (id) {
case FOURCC_YV12:
case FOURCC_I420:
printk("[%s]YUV420\n", __func__);
#if 0
/* set UV vertical phase to -0.25 */
overlay->UV_VPH = 0x30003000;
#endif
printk("[%s]UV stride is %d, Y stride is %d\n", __func__,
dstPitch, dstPitch * 2);
overlay->OSTRIDE = (dstPitch * 2) | (dstPitch << 16);
OCMD &= ~SOURCE_FORMAT;
OCMD &= ~OV_BYTE_ORDER;
OCMD |= YUV_420;
break;
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
printk("[%s]YUV422\n", __func__);
overlay->OSTRIDE = dstPitch;
OCMD &= ~SOURCE_FORMAT;
OCMD |= YUV_422;
OCMD &= ~OV_BYTE_ORDER;
if (id == FOURCC_UYVY)
OCMD |= Y_SWAP;
break;
}
OCMD &= ~(BUFFER_SELECT | FIELD_SELECT);
if (pPriv->currentBuf == 0)
OCMD |= BUFFER0;
else
OCMD |= BUFFER1;
overlay->OCMD = OCMD;
//printk("[%s]OCMD is 0x%" PRIx32 "\n", __func__, OCMD);
#if 0 //kscho
/* make sure the overlay is on */
intel_overlay_on (dinfo);
/* and show this frame */
intel_overlay_continue (dinfo, scaleChanged);
#endif
printk("[%s]leave\n", __func__);
}
#if 1
static int intel_display_surface(struct intelfb_info *dinfo,
short src_x, short src_y,
short drw_x, short drw_y,
short src_w, short src_h,
short drw_w, short drw_h)
//, RegionPtr clipBoxes)
{
int32_t x1, y1, x2, y2;
BoxRec dstBox;
printk("[%s]IntelDisplaySurface enter %p\n", __func__, dinfo);
x1 = src_x;
x2 = src_x + src_w;
y1 = src_y;
y2 = src_y + src_h;
dstBox.x1 = drw_x;
dstBox.x2 = drw_x + drw_w;
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
/* fixup pointers */
#if 0
pI830Priv->YBuf0offset = surface->offsets[0];
pI830Priv->YBuf1offset = pI830Priv->YBuf0offset;
#else
#endif
printk("[%s]dstBox x1:%d, x2:%d, y1:%d, y2:%d\n", __func__, dstBox.x1,
dstBox.x2, dstBox.y1, dstBox.y2);
intel_display_video(dinfo, FOURCC_YV12, 800, 600, 0, x1, y1, x2,
y2, &dstBox, src_w, src_h, drw_w, drw_h);
printk("[%s]leave\n", __func__);
}
#endif
static uint32_t I830BoundGammaElt (uint32_t elt, uint32_t eltPrev)
{
elt &= 0xff;
eltPrev &= 0xff;
if (elt < eltPrev)
elt = eltPrev;
else if ((elt - eltPrev) > 0x7e)
elt = eltPrev + 0x7e;
return elt;
}
static uint32_t I830BoundGamma (uint32_t gamma, uint32_t gammaPrev)
{
return (I830BoundGammaElt (gamma >> 24, gammaPrev >> 24) << 24 |
I830BoundGammaElt (gamma >> 16, gammaPrev >> 16) << 16 |
I830BoundGammaElt (gamma >> 8, gammaPrev >> 8) << 8 |
I830BoundGammaElt (gamma , gammaPrev ));
}
static void intel_update_gamma(struct intelfb_info *dinfo)
{
IntelPortPrivPtr pPriv;
pPriv = &g_Priv;
uint32_t gamma0, gamma1, gamma2, gamma3, gamma4, gamma5;
printk("[%s]enter\n", __func__);
gamma0 = pPriv->gamma0;
gamma1 = pPriv->gamma1;
gamma2 = pPriv->gamma2;
gamma3 = pPriv->gamma3;
gamma4 = pPriv->gamma4;
gamma5 = pPriv->gamma5;
gamma1 = I830BoundGamma (gamma1, gamma0);
gamma2 = I830BoundGamma (gamma2, gamma1);
gamma3 = I830BoundGamma (gamma3, gamma2);
gamma4 = I830BoundGamma (gamma4, gamma3);
gamma5 = I830BoundGamma (gamma5, gamma4);
OUTREG(OGAMC5, gamma5);
OUTREG(OGAMC4, gamma4);
OUTREG(OGAMC3, gamma3);
OUTREG(OGAMC2, gamma2);
OUTREG(OGAMC1, gamma1);
OUTREG(OGAMC0, gamma0);
printk("[%s]leave\n", __func__);
}
static IntelPortPrivPtr intel_setup_video_overlay(struct intelfb_info
*dinfo )
{
IntelPortPrivPtr pPriv;
pPriv = &g_Priv;
DBG_MSG("[%s]enter %p\n", __func__, dinfo);
pPriv->textured = FALSE;
#if 0 //kscho for temp
pPriv->colorKey = pI830->colorKey & ((1 << pScrn->depth) - 1);
#else
pPriv->colorKey = 0;
#endif
pPriv->videoStatus = 0;
pPriv->brightness = 0;
pPriv->contrast = 64;
pPriv->saturation = 128;
#if 0 //kscho
pPriv->current_crtc = NULL;
pPriv->desired_crtc = NULL;
pPriv->buf = NULL;
#endif
pPriv->currentBuf = 0;
pPriv->gamma5 = 0xc0c0c0;
pPriv->gamma4 = 0x808080;
pPriv->gamma3 = 0x404040;
pPriv->gamma2 = 0x202020;
pPriv->gamma1 = 0x101010;
pPriv->gamma0 = 0x080808;
pPriv->doubleBuffer = 1;
/* With LFP's we need to detect whether we're in One Line Mode,
which
* essentially means a resolution greater than 1024x768, and fix up
* the scaler accordingly. */
pPriv->scaleRatio = 0x10000;
pPriv->oneLineMode = FALSE;
/*
* Initialise pPriv->overlayOK. Set it to TRUE here so that a
warning will
* be generated if i830_crtc_dpms_video() sets it to FALSE during
mode
* setup.
*/
pPriv->overlayOK = TRUE;
intel_reset_video();
intel_update_gamma(dinfo);
DBG_MSG("[%s]leave\n", __func__);
return pPriv;
}
static void intel_overlay_test(struct intelfb_info *dinfo)
{
IntelOverlayRegPtr overlay;
int width = 800;
int height = 600;
overlay = &g_overlay;
overlay->SWIDTH = width | ((width/2 & 0x7ff) << 16);
overlay->SHEIGHT = height | ((height / 2) << 16);
START_RING(6);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
OUT_RING(MI_NOOP);
OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
OUT_RING(overlay);
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
OUT_RING(MI_NOOP);
ADVANCE_RING();
}
static int intelvid_ioctl(struct inode *inode, struct file *file, unsigned
int cmd, unsigned long arg)
{
printk("[%s]enter\n", __func__);
if( _IOC_TYPE( cmd ) != INTELVID_MAGIC) {
return -EINVAL;
}
switch(cmd){
case INTELVID_OVERLAY_ON:
DBG_MSG("INTELVID_OVERLAY_ON\n");
break;
case INTELVID_OVERLAY_OFF:
DBG_MSG("INTELVID_OVERLAY_OFF\n");
break;
case INTELVID_OVERLAY_SRC_RECT:
DBG_MSG("INTELVID_SRC_RECT\n");
break;
case INTELVID_OVERLAY_DST_RECT:
DBG_MSG("INTELVID_DST_RECT\n");
break;
case INTELVID_OVERLAY_COLORKEY:
DBG_MSG("INTELVID_COLORKEY\n");
break;
case INTELVID_OVERLAY_DISPREG:
DBG_MSG("INTELVID_OVERLAY_DISPREG\n");
intel_compare_overlay(g_dinfo);
break;
case INTELVID_OVERLAY_TEST:
DBG_MSG("INTELVID_OVERLAY_TEST\n");
intel_overlay_test(g_dinfo);
break;
default:
return -ENOTTY;
}
printk("[%s]leave\n", __func__);
return 0;
}
static int intelvid_mmap(struct file *file, struct vm_area_struct *vma)
{
return 0;
}
static int intelvid_open(struct inode *inode, struct file *file)
{
return 0;
}
static int intelvid_release(struct inode *inode, struct file *file)
{
return 0;
}
static struct file_operations intelvid_fops =
{
.ioctl = intelvid_ioctl,
.mmap = intelvid_mmap,
.open = intelvid_open,
.release = intelvid_release
};
static void cleanup(struct intelfb_info *dinfo)
{
if (!dinfo)
return;
// unset_mtrr(dinfo);
if (dinfo->mmio_base)
iounmap((void __iomem *)dinfo->mmio_base);
if (dinfo->aperture.virtual)
iounmap((void __iomem *)dinfo->aperture.virtual);
framebuffer_release(dinfo->info);
}
static int __devinit intelfb_pci_register(struct pci_dev *pdev, const
struct pci_device_id *ent)
{
struct fb_info *info;
struct intelfb_info *dinfo;
int i, err, dvo;
int aperture_size, stolen_size;
struct agp_kern_info gtt_info;
int agp_memtype;
const char *s;
struct agp_bridge_data *bridge;
int aperture_bar = 0;
int mmio_bar = 1;
int offset;
DBG_MSG("intelfb_pci_register\n");
info = framebuffer_alloc(sizeof(struct intelfb_info), &pdev->dev);
if (!info) {
ERR_MSG("Could not allocate memory for intelfb_info.\n");
return -ENODEV;
}
if (fb_alloc_cmap(&info->cmap, 256, 1) < 0) {
ERR_MSG("Could not allocate cmap for intelfb_info.\n");
goto err_out_cmap;
return -ENODEV;
}
printk("[%s:%d]intel\n", __func__, __LINE__);
dinfo = info->par;
dinfo->info = info;
#if 0 //kscho
dinfo->fbops = &intel_fb_ops;
#else
//dinfo->fbops = &intelvid_fops;
#endif
dinfo->pdev = pdev;
/* Reserve pixmap space. */
info->pixmap.addr = kzalloc(64 * 1024, GFP_KERNEL);
if (info->pixmap.addr == NULL) {
//ERR_MSG("Cannot reserve pixmap memory.\n");
printk(KERN_ERR"Cannot reserve pixmap memory.\n");
goto err_out_pixmap;
}
/* set early this option because it could be changed by tv encoder
driver */
dinfo->fixed_mode = fixed;
/* Enable device. */
if ((err = pci_enable_device(pdev))) {
//ERR_MSG("Cannot enable device.\n");
printk(KERN_ERR"Cannot enable device.\n");
cleanup(dinfo);
return -ENODEV;
}
/* Set base addresses. */
if ((ent->device == PCI_DEVICE_ID_INTEL_915G) ||
(ent->device == PCI_DEVICE_ID_INTEL_915GM) ||
(ent->device == PCI_DEVICE_ID_INTEL_945G) ||
(ent->device == PCI_DEVICE_ID_INTEL_945GM)) {
aperture_bar = 2;
mmio_bar = 0;
}
dinfo->aperture.physical = pci_resource_start(pdev, aperture_bar);
dinfo->aperture.size = pci_resource_len(pdev, aperture_bar);
printk("[%s:%d]>>aperture physical:%p, size:%d\n", __func__,
__LINE__, dinfo->aperture.physical, dinfo->aperture.size );
dinfo->mmio_base_phys = pci_resource_start(pdev, mmio_bar);
printk("fb aperture: 0x%llx/0x%llx, MMIO region: 0x%llx/0x%llx\n",
(unsigned long long)pci_resource_start(pdev, aperture_bar),
(unsigned long long)pci_resource_len(pdev, aperture_bar),
(unsigned long long)pci_resource_start(pdev, mmio_bar),
(unsigned long long)pci_resource_len(pdev, mmio_bar));
#if 0 //kscho
/* Reserve the fb and MMIO regions */
if (!request_mem_region(dinfo->aperture.physical, dinfo-
>aperture.size,
INTELFB_MODULE_NAME)) {
ERR_MSG("Cannot reserve FB region.\n");
cleanup(dinfo);
return -ENODEV;
}
dinfo->flag |= INTELFB_FB_ACQUIRED;
if (!request_mem_region(dinfo->mmio_base_phys,
INTEL_REG_SIZE,
INTELFB_MODULE_NAME)) {
ERR_MSG("Cannot reserve MMIO region.\n");
cleanup(dinfo);
return -ENODEV;
}
dinfo->flag |= INTELFB_MMIO_ACQUIRED;
#endif
/* Get the chipset info. */
dinfo->pci_chipset = pdev->device;
#if 1 //kscho added
g_IntelRec.PciInfo = pdev->device;
#endif
if (intelfbhw_get_chipset(pdev, dinfo)) {
cleanup(dinfo);
return -ENODEV;
}
if (intelfbhw_get_memory(pdev, &aperture_size,&stolen_size)) {
cleanup(dinfo);
return -ENODEV;
}
INF_MSG("%02x:%02x.%d: %s, aperture size %dMB, "
"stolen memory %dkB\n",
pdev->bus->number, PCI_SLOT(pdev->devfn),
PCI_FUNC(pdev->devfn), dinfo->name,
BtoMB(aperture_size), BtoKB(stolen_size));
/* Set these from the options. */
dinfo->accel = accel;
dinfo->hwcursor = hwcursor;
if (NOACCEL_CHIPSET(dinfo) && dinfo->accel == 1) {
INF_MSG("Acceleration is not supported for the %s
chipset.\n",
dinfo->name);
dinfo->accel = 0;
}
/* Framebuffer parameters - Use all the stolen memory if >= vram */
if (ROUND_UP_TO_PAGE(stolen_size) >= MB(vram)) {
dinfo->fb.size = ROUND_UP_TO_PAGE(stolen_size);
dinfo->fbmem_gart = 0;
} else {
dinfo->fb.size = MB(vram);
dinfo->fbmem_gart = 1;
}
/* Allocate space for the ring buffer and HW cursor if enabled. */
if (dinfo->accel) {
dinfo->ring.size = RINGBUFFER_SIZE;
dinfo->ring_tail_mask = dinfo->ring.size - 1;
}
if (dinfo->hwcursor){
dinfo->cursor.size = HW_CURSOR_SIZE;
}
#if 0 //kscho
/* Use agpgart to manage the GATT */
if (!(bridge = agp_backend_acquire(pdev))) {
ERR_MSG("cannot acquire agp\n");
cleanup(dinfo);
return -ENODEV;
}
#else
if (!(bridge = agp_find_bridge(pdev))) {
ERR_MSG("cannot find agp\n");
cleanup(dinfo);
return -ENODEV;
}
#endif
/* get the current gatt info */
if (agp_copy_info(bridge, >t_info)) {
ERR_MSG("cannot get agp info\n");
//agp_backend_release(bridge);
cleanup(dinfo);
return -ENODEV;
}
printk("[%s:%d]voffset:%d\n", __func__, __LINE__, voffset);
if (MB(voffset) < stolen_size)
offset = (stolen_size >> 12);
else
offset = ROUND_UP_TO_PAGE(MB(voffset))/GTT_PAGE_SIZE;
/* set the mem offsets - set them after the already used pages */
if (dinfo->accel)
dinfo->ring.offset = offset + gtt_info.current_memory;
if (dinfo->hwcursor) {
dinfo->cursor.offset = offset +
+ gtt_info.current_memory + (dinfo->ring.size >>
12);
}
if (dinfo->fbmem_gart) {
dinfo->fb.offset = offset +
+ gtt_info.current_memory + (dinfo->ring.size >> 12)
+ (dinfo->cursor.size >> 12);
}
/* Allocate memories (which aren't stolen) */
/* Map the fb and MMIO regions */
/* ioremap only up to the end of used aperture */
#if 1
dinfo->aperture.virtual = (u8 __iomem *)ioremap_nocache
(dinfo->aperture.physical, ((offset + dinfo->fb.offset) <<
12) + dinfo->fb.size);
#else
dinfo->aperture.virtual = (u8 __iomem *)ioremap_nocache
(dinfo->aperture.physical, 131072);
#endif
if (!dinfo->aperture.virtual) {
ERR_MSG("Cannot remap FB region.\n");
cleanup(dinfo);
return -ENODEV;
}
dinfo->mmio_base =
(u8 __iomem *)ioremap_nocache(dinfo->mmio_base_phys,
INTEL_REG_SIZE);
if (!dinfo->mmio_base) {
ERR_MSG("Cannot remap MMIO region.\n");
cleanup(dinfo);
return -ENODEV;
}
if(dinfo->accel){
printk("[%s:%d]dinfo->accel\n", __func__, __LINE__);
#if 1
if (!(dinfo->gtt_ring_mem =
agp_allocate_memory(bridge, dinfo->ring.size >> 12,
AGP_NORMAL_MEMORY))) {
ERR_MSG("cannot allocate ring buffer memory\n");
agp_backend_release(bridge);
cleanup(dinfo);
return -ENOMEM;
}
if (agp_bind_memory(dinfo->gtt_ring_mem,
dinfo->ring.offset)) {
ERR_MSG("cannot bind ring buffer memory\n");
agp_backend_release(bridge);
cleanup(dinfo);
return -EBUSY;
}
#endif
dinfo->ring.physical = dinfo->aperture.physical
+ (dinfo->ring.offset << 12);
dinfo->ring.virtual = dinfo->aperture.virtual
+ (dinfo->ring.offset << 12);
dinfo->ring_head = 0;
}
if (dinfo->hwcursor) {
DBG_MSG("dinfo->hwcursor\n");
#if f
agp_memtype = dinfo->mobile ? AGP_PHYSICAL_MEMORY
: AGP_NORMAL_MEMORY;
if(agp_memtype == AGP_PHYSICAL_MEMORY){
DBG_MSG("dinfo->hwcursor AGP_PHYSICAL_MEMORY\n");
}else{
DBG_MSG("dinfo->hwcursor AGP_NORMAL_MEMORY\n");
}
if (!(dinfo->gtt_cursor_mem =
agp_allocate_memory(bridge, dinfo->cursor.size >> 12,
agp_memtype))) {
ERR_MSG("cannot allocate cursor memory\n");
agp_backend_release(bridge);
cleanup(dinfo);
return -ENOMEM;
}
if (agp_bind_memory(dinfo->gtt_cursor_mem,
dinfo->cursor.offset)) {
ERR_MSG("cannot bind cursor memory\n");
agp_backend_release(bridge);
cleanup(dinfo);
return -EBUSY;
}
if (dinfo->mobile)
dinfo->cursor.physical
= dinfo->gtt_cursor_mem->physical;
else
dinfo->cursor.physical = dinfo->aperture.physical
+ (dinfo->cursor.offset << 12);
dinfo->cursor.virtual = dinfo->aperture.virtual
+ (dinfo->cursor.offset << 12);
#endif
}
#if 0 //kscho, 2008/11/14
if (dinfo->fbmem_gart) {
if (!(dinfo->gtt_fb_mem =
agp_allocate_memory(bridge, dinfo->fb.size >> 12,
AGP_NORMAL_MEMORY))) {
WRN_MSG("cannot allocate framebuffer memory - use "
"the stolen one\n");
dinfo->fbmem_gart = 0;
}
if (agp_bind_memory(dinfo->gtt_fb_mem,
dinfo->fb.offset)) {
WRN_MSG("cannot bind framebuffer memory - use "
"the stolen one\n");
dinfo->fbmem_gart = 0;
}
}
#endif
/* update framebuffer memory parameters */
if (!dinfo->fbmem_gart){
dinfo->fb.offset = 0; /* starts at offset 0 */
printk("[%s]starts at offset 0\n", __func__);
}
dinfo->fb.physical = dinfo->aperture.physical
+ (dinfo->fb.offset << 12);
dinfo->fb.virtual = dinfo->aperture.virtual + (dinfo->fb.offset <<
12);
dinfo->fb_start = dinfo->fb.offset << 12;
/* release agpgart */
agp_backend_release(bridge);
#if 1
if (mtrr)
set_mtrr(dinfo);
#endif
DBG_MSG("fb: 0x%x(+ 0x%x)/0x%x (0x%p)\n",
dinfo->fb.physical, dinfo->fb.offset, dinfo->fb.size,
dinfo->fb.virtual);
DBG_MSG("MMIO: 0x%x/0x%x (0x%p)\n",
dinfo->mmio_base_phys, INTEL_REG_SIZE,
dinfo->mmio_base);
DBG_MSG("ring buffer: 0x%x/0x%x (0x%p)\n",
dinfo->ring.physical, dinfo->ring.size,
dinfo->ring.virtual);
DBG_MSG("HW cursor: 0x%x/0x%x (0x%p) (offset 0x%x) (phys 0x%x)\n",
dinfo->cursor.physical, dinfo->cursor.size,
dinfo->cursor.virtual, dinfo->cursor.offset,
dinfo->cursor.physical);
DBG_MSG("options: vram = %d, accel = %d, hwcursor = %d, fixed = %d,
"
"noinit = %d\n", vram, accel, hwcursor, fixed, noinit);
DBG_MSG("options: mode = \"%s\"\n", mode ? mode : "");
pci_set_drvdata(pdev, dinfo);
g_dinfo = dinfo;
#if 0
/* 2d acceleration init */
if (dinfo->accel){
//intelfbhw_2d_stop(dinfo);
intelfbhw_2d_start(dinfo);
}
#endif
#if 1
//kscho
intel_compare_overlay(dinfo);
//intel_setup_video_overlay(dinfo);
//intel_display_surface(dinfo, 0, 0, 0, 0, 640, 480, 800, 600);
//intel_compare_overlay(dinfo);
#endif
return 0;
err_out_pixmap:
fb_dealloc_cmap(&info->cmap);
err_out_cmap:
framebuffer_release(info);
return -ENODEV;
}
static void __devexit intelfb_pci_unregister(struct pci_dev *pdev)
{
struct intelfb_info *dinfo = pci_get_drvdata(pdev);
DBG_MSG("[%s]enter\n", __func__);
if (!dinfo)
return;
cleanup(dinfo);
pci_set_drvdata(pdev, NULL);
DBG_MSG("[%s]leave\n", __func__);
}
static struct pci_driver intelvid_driver = {
.name = "intelvid",
.id_table = intelfb_pci_table,
.probe = intelfb_pci_register,
.remove = __devexit_p(intelfb_pci_unregister),
};
int __init init_module(void)
{
int ret;
ret = pci_register_driver(&intelvid_driver);
if(ret < 0){
printk("intel_vid pci register failed\n");
return ret;
}
#if 1
printk("before intel_vid register_chrdev \n");
ret = register_chrdev(INTELVID_MAJOR, INTELVID_NAME,
&intelvid_fops);
if(ret < 0){
printk("intel_vid register_chrdev failed\n");
return ret;
}
#endif
}
void __exit cleanup_module(void)
{
pci_unregister_driver(&intelvid_driver);
unregister_chrdev(INTELVID_MAJOR, INTELVID_NAME);
}
---------------------------------------------------------------------
6F Lotte IT Castle II 550-1 Gasan-dong,
Geumcheon-gu, Seoul, 153-768, Korea
Research Engineer/R&D software Team
Tel: 82-2-890-1657(Direct)
FAX:02-890-1639
_______________________________________________
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