I think this should be caused by qemu-accel* used during build. I can see in the build config of Tizen:Common, qemu-accel-armv7l is used, but actually it should be qemu-accel-armv7l-cross-arm, which contains the following post script command line:
post "builtin echo 0 >/proc/sys/vm/mmap_min_addr" Which should be the actually fix code. Please refer to Tizen:Mobile project: https://build.tizen.org/project/prjconf?project=Tizen%3AMobile Thanks Qiang From: Dev [mailto:[email protected]] On Behalf Of Dominig ar Foll (Intel OTC) Sent: Wednesday, May 21, 2014 12:33 AM To: [email protected] Subject: [Dev] Help needed to progress ARM build for Tizen3 Hello, we are facing some difficulties in re-boot strapping Tizen3 Common for ARM. We did an initial bootstrap using Tizen Mobile and that has allowed us to build almost all Tizen3 Common packages (only 8 out of 738 are still not building). But now in order to get a clean built, we want to self-re-bootstrap the ARM repo and we are facing difficulties with glibc and a few other packages. We would need help to fix the glibc build issue first as we expect that the same fix will work for the other packages. Our configuration uses OBS workers with KVM. Our build issue can be seen here: https://build.tizen.org/package/live_build_log?arch=armv7l&package=glibc&project=Tizen%3ACommon&repository=arm-wayland The error is very strange: /home/abuild/rpmbuild/BUILD/glibc-2.18/cc-base/iconv/iconvconfig: error while loading shared libraries: /home/abuild/rpmbuild/BUILD/glibc-2.18/cc-base/iconv/iconvconfig: failed to map segment from shared object: Operation not permitted We think that the error is due to a package that is missing in a alternative architecture (e.g. IA32) during the boot strap process and the sharelib load fails due to the Arch mismatch but we might be wrong. We have no clue on how to correct the issue. Do you have any idea how to progress ? Does someone know how to bootstrap ARM on an OBS ? Thanks in advance for your help. -- Dominig ar Foll Senior Software Architect Open Source Technology Centre Intel SSG
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