Thanks Alan! Nope sorry I haven't tested on Sipeed M1s, I should get it someday.
I'm preparing a PR that will extend the RISC-V MMU Flags from 32-bit to 64-bit, because: (1) T-Head C906 (BL808) needs us to set Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered (2) Newer RISC-V Cores will use the Svpbmt Extension (Bits 61 to 62) to configure the Memory Type (Cacheable / Strongly-Ordered) More about Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt Lup On Sun, Dec 10, 2023 at 10:04 PM Alan C. Assis <acas...@gmail.com> wrote: > Hi Lup, > > Nice to know you found the issue (and Linux errata for T-Head C906 helped), > that BUG is really strange. > > Probably a similar issue could exist on MILK-V board too. > > Did you test NuttX on Sipeed M1s Dock AI + IoT BL808 RISC-V? > > Unfortunately Pine 0x64 doesn't ship to Brazil (probably many buyers let > the boards return after getting notified of higher taxes from Brazilian > Customs). > > Best Regards, > > Alan > > On Sat, Dec 9, 2023 at 8:11 PM Lee, Lup Yuen <lu...@appkaki.com> wrote: > > > Last week we walked through the Serial Console for Pine64 Ox64 BL808 > 64-bit > > RISC-V Single-Board Computer. And we hit some illogical impossible > problems > > on NuttX for Ox64: > > > > (1) Console Input is always empty. (Can’t enter any Console Commands) > > (2) Interrupt Claim is forever 0. (Ox64 won’t tell us which Interrupt was > > fired!) > > (3) Leaky Writes are mushing up adjacent Interrupt Registers. (Or maybe > > Leaky Reads?) > > > > Today we discover the One Single Culprit behind all this rowdy mischief: > > Weak Ordering in the MMU! (Memory Management Unit) > > > > Here’s how we solved the baffling mystery: > > https://lupyuen.codeberg.page/articles/plic3.html > > > > Lup > > >
