Let's follow the discussion here to avoid polluting the previous thread.
On 2/18/24, Tomek CEDRO <to...@cedro.info> wrote: > Closed, okay, and the FPGA part did not get in? > > -- > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > On Sun, Feb 18, 2024 at 10:17 PM Alan C. Assis <acas...@gmail.com> wrote: >> >> Hi Tomek, >> Thank you for raising these concerns. >> >> BTW, I suggest you change the Subject to something related to NuttX and >> FPGA, since the GSoC 2024 proposal is already closed (on Feb 6). >> >> Best Regards, >> >> Alan >> >> On Sun, Feb 18, 2024 at 4:52 PM Tomek CEDRO <to...@cedro.info> wrote: >> >> > After some more considerations I am pro this "generic" NuttX@FPGA >> > Reference Design on GSoC proposal, 10 resons below :-) >> > >> > I kindly ask to add this one to the proposals list :-) >> > >> > 1. We do not have a reference FPGA design for NuttX. >> > 2. We do not have a reference fully Open-Source toolchain for >> > FPGA+NuttX. >> > 3. Yes someone did that before, and anyone can do that, but we can >> > provide generic out-of-the-box solution that most people are looking >> > for. Creating / repeating one yourself costs time. >> > 4. We can gather smart community around NuttX that way (i.e. Victor). >> > 5. FPGA are getting smaller and cheaper close to a price range of MCU >> > (i.e. $5+) [1][2]. >> > 6. FPGA has big advantage over MCU in peripheral speed (mainly GPIO >> > nMHz vs nnnMHz). I can see unique benefit for having custom >> > peripherals created that way. I once did an R&D on new type of ADC >> > where MCU GPIO was not fast enough and I have to switch to FPGA + >> > external control MCU board. >> > 7. Using propietary tools was quite painful because I had to use big >> > Xilinx Vivado while there are fully Open-Source toolchains already out >> > there we can use like Yosys / OSS CAD Suite [3] etc. >> > 8. Scaling to bigger FPGA gives more possibilities like new >> > architecture testing (i.e. RISC-V 128-bit or tens/hundreds of cores) >> > [4], emulation [5], machine learning, etc. >> > 9. My initial proposal was highly experimental and could easily fail. >> > Victor's proposal is merit and result based. It will for sure serve >> > many people out there for bigger and smaller projects. >> > 10. Other ideas like Xorg port could be tested on FPGA implementation >> > too.. I already saw Victor's working windows manager with >> > chip-mod-player running on FPGA :-) >> > >> > I can be mentor of that project because I would like to grow in that >> > field too as I have some ideas to test :-) >> > >> > Thanks for considering :-) >> > Tomek >> > >> > [1] https://tinyfpga.com/ >> > [2] >> > https://www.cnx-software.com/2019/10/15/5-tang-nano-fpga-board-gowin-gw1n-littlebee-fpga/ >> > [3] https://github.com/YosysHQ/oss-cad-suite-build >> > [4] >> > https://riscv.org/news/2021/08/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator-sally-ward-foxton-ee-times/ >> > [5] https://www.retrorgb.com/mister.html >> > >> > -- >> > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >> > >> > On Sat, Jan 27, 2024 at 10:58 PM Victor Suarez Rovere >> > <suarezvic...@gmail.com> wrote: >> > > >> > > The innovation won't be to run NuttX in a RISC-V (soft-core or not) >> > > but >> > > using a FPGA for its flexibility to add any kind of peripherals, one >> > > of >> > the >> > > main ones to be useful in my view will be a high-resolution >> > > framebuffer >> > and >> > > USB mouse/keyboard for a complete UI >> > > >> > > On Sat, Jan 27, 2024 at 4:31 PM Gregory Nutt <spudan...@gmail.com> >> > wrote: >> > > >> > > > Aren't most CPUs available as soft cores? Certainly Xtensa was >> > intended >> > > > for that purpose. ARM and MIPS have been common soft cores in >> > > > ASICs >> > for >> > > > more than a decade. As is RISC-V soft core in FPGAs. >> > > > https://en.wikipedia.org/wiki/Soft_microprocessor >> > > > >> > > > In the past, there was some interest in ports of NuttX to >> > > > softcore's >> > > > like MicroBlaze. But there hasn't been that kind of interest in >> > > > recent >> > > > times. >> > > > >> > > > This would have been an innovation a decade or so ago, but I wonder >> > > > about that now. >> > > > >> > > > >> > > > >> > > > On 1/27/2024 1:18 PM, Victor Suarez Rovere wrote: >> > > > > Tomek, as I clarified, porting NuttX to a FPGA will require a >> > soft-core >> > > > > CPU. I don't envision an opertaing system without a CPU, I see >> > > > > that >> > like >> > > > a >> > > > > bad design choice if possible at all >> > > > > Using a soft core and custom peripherals seems more valuable, >> > > > > even >> > > > > including video output and USB host for mouse/keyboard handling. >> > > > > I've >> > > > done >> > > > > that for Micropython >> > > > > >> > > > > El sáb., 27 ene. 2024 13:23, Tomek CEDRO <to...@cedro.info> >> > escribió: >> > > > > >> > > > >> Okay Victor, I was thinking about toolchain that you present in >> > > > >> "Sphery vs. Shapes" [1] to be adopted for NuttX on FPGA >> > > > >> conversion >> > > > >> without a CPU design.. could you please send your full detailed >> > > > >> proposal then? :-) >> > > > >> >> > > > >> [1] https://www.youtube.com/watch?v=hn3sr3VMJQU >> > > > >> >> > > > >> -- >> > > > >> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >> > > > >> >> > > > >> On Sat, Jan 27, 2024 at 7:22 AM Victor Suarez Rovere >> > > > >> <suarezvic...@gmail.com> wrote: >> > > > >>> Just clarifying, the idea to run NuttX on a FPGA is to >> > > > >>> instantiate >> > a >> > > > CPU >> > > > >>> and peripherals on the FPGA and then run normally as if it were >> > > > >>> a >> > MCU >> > > > >>> Good thing is that you can change the CPU, add/remove >> > > > >>> peripherals, >> > etc. >> > > > >>> >> > > > >>> On Sat, Jan 27, 2024 at 12:32 AM Tomek CEDRO <to...@cedro.info> >> > wrote: >> > > > >>> >> > > > >>>> Hey there Victor! Thanks for your interest in NuttX port to >> > FPGA!! :-) >> > > > >>>> >> > > > >>>> No there is no such design yet.. you would have to create >> > everything >> > > > >>>> from scratch.. so there is some serious amount of work to do.. >> > > > >>>> but >> > > > >>>> imagine the results.. there will be just one step to ASIC!! >> > > > >>>> :-) >> > > > >>>> >> > > > >>>> I could reconsider my mentor position in this kind of project >> > because >> > > > >>>> I would really love to see the internals first hand.. with a >> > > > >>>> help >> > of >> > > > >>>> more experienced NuttX'er for sure as second mentor :-) :-) >> > > > >>>> >> > > > >>>> I did a PONG on FPGA over 10 years ago but I would never dare >> > > > >>>> to >> > run >> > > > >>>> CPU-less-program directly on FPGA.. then RTOS.. then lets say >> > Atari >> > > > >>>> emulator.. chip module player.. open source smart debug probe.. >> > > > >>>> a >> > > > >>>> neural interface.. who knows.. would that even fit into the >> > > > >>>> FPGA? >> > :-) >> > > > >>>> :-) >> > > > >>>> >> > > > >>>> I have a strong feeling this may be important.. but I leave >> > > > >>>> the >> > whole >> > > > >>>> decision to the PMC :-) >> > > > >>>> >> > > > >>>> Have a good weekend my friends :-) >> > > > >>>> Tomek >> > > > >>>> >> > > > >>>> -- >> > > > >>>> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >> > > > >>>> >> > > > >>>> On Sat, Jan 27, 2024 at 2:55 AM Victor Suarez Rovere >> > > > >>>> <suarezvic...@gmail.com> wrote: >> > > > >>>>> I can certainly port NuttX to run on some FPGA boards too >> > > > >>>>> Is any board already supported? >> > > > >>>>> >> > > > >>>>> On Fri, Jan 26, 2024 at 4:40 PM Alan C. Assis >> > > > >>>>> <acas...@gmail.com >> > > >> > > > >> wrote: >> > > > >>>>>> Hi Tomek, >> > > > >>>>>> >> > > > >>>>>> His toolchain is focused on FPGA, but he is interested in >> > > > >>>> participating in >> > > > >>>>>> other projects for GSoC. >> > > > >>>>>> >> > > > >>>>>> Also we need NuttX mentors, I will participate, but for each >> > > > >> project we >> > > > >>>>>> need two mentors, please let me know who could be interested >> > > > >>>>>> to >> > > > >> help. >> > > > >>>>>> Best Regards, >> > > > >>>>>> >> > > > >>>>>> Alan >> > > > >>>>>> >> > > > >>>>>> On Fri, Jan 26, 2024 at 3:33 PM Tomek CEDRO >> > > > >>>>>> <to...@cedro.info> >> > > > >> wrote: >> > > > >>>>>>> On Fri, Jan 26, 2024 at 2:07 PM Alan C. Assis wrote: >> > > > >>>>>>>> Dear NuttXers, >> > > > >>>>>>>> Please find below some ideas of projects to improve NuttX >> > > > >> during >> > > > >>>> the >> > > > >>>>>>>> GSoC2024: >> > > > >>>>>>>> >> > > > >> >> > https://cwiki.apache.org/confluence/display/COMDEV/GSoC+2024+Ideas+list >> > > > >>>>>>>> If you have some other ideas, please let me know. >> > > > >>>>>>> I would like to propose Victor Suarez (CC) idea for porting >> > > > >> toolchain >> > > > >>>>>>> NuttX RTOS directly to FPGA :-) >> > > > >>>>>>> >> > > > >>>>>>> >> > > > >>>>>>> >> > > > >> >> > > > >> > https://www.tomshardware.com/news/fpga-demo-shows-efficiency-gains-compared-to-x86-chip >> > > > >>>>>>> Tomek >> > > > >>>>>>> >> > > > >>>>>>> -- >> > > > >>>>>>> CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >> > > > >>>>>>> >> > > > >> > > > >> > >
