Very interesting book upcoming soon on RISC-V :-)
https://www.youtube.com/watch?v=Qyq5nHUDt4g
Recorded session from RISC-V's Academic and Training SIG meeting on
Thursday, June 5 at 8 AM PT. We heard from David Harris, Sarah Harris,
James Stine and Rose Thompson about their upcoming textbook.
>From the Authors:
We introduce our new textbook, RISC-V System-on-Chip Design, which
will be published in the next few months. It fits at the nexus of
computer architecture, microarchitecture, and chip design and bridges
the gap between theory and practice. The book:
Teaches computer architecture principles & practices
Concrete application & implementation of the open RISC-V architecture
Explores rarely taught microarchitectural issues
Pipelines, buses, caches, branch prediction, virtual memory,
floating-point, cryptography & peripherals
Illustrates system design with CORE-V Wally, a fully functional
RISC-V system-on-chip
Programming & debugging RISC-V in C & assembly
SystemVerilog design, debug, verification & synthesis
Benchmarking
Booting Linux on a simulator & FPGA
Includes complete open-source code at: github.com/openhwgroup/cvw
About the book:
RISC-V Microprocessor System-On-Chip Design is written to be
accessible to an advanced undergraduate audience with limited
background. It explains concepts from operating systems, VLSI, and
memory systems as necessary, and High school mathematics is sufficient
preparation for most of the book, although the floating point and
division chapters will be primarily of interest to those with a
curiosity about computer arithmetic. Like Harris and Harris’s Digital
Design and Computer Architecture textbooks, this book will appeal to
students with easy-to-read and complete explanations, sidebars, and
occasional humor and cartoons.
It comes with an open-source implementation and will include
end-of-chapter problems to extend the RISC-V processor in various
ways. Ancillary materials include a GitHub repository with complete
open-source SystemVerilog code, validation code in C and assembly
language, and code for benchmarking and booting Linux.
Covers detailed design for all components of a nontrivial microprocessor
Provides detailed explanations on the implementation of RISC-V microprocessors
Uses open-source SystemVerilog code and test cases for the entire
processor, including single-issue and superscalar cores, multicore,
all extensions (including multiplication/division, floating point, and
atomic memory operations), and common peripherals
Enables users to build scripts to implement the processor on the
open-source Skywater process
Preorder available at Amazon ($105 Kindle, $125 Paper):
https://www.amazon.com/dp/0323994989
But I also found it at Elsevier shop directly with 50% discount for
$112.5 paper+ebook bundle and free global shipping:
https://shop.elsevier.com/books/risc-v-system-on-chip-design/harris/978-0-323-99498-9
--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
