FYI :-) -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
---------- Forwarded message --------- From: Mr Iain Robertson via lists.riscv.org Date: Mon, Jan 12, 2026 at 12:33 PM Subject: [RISC-V tech-announce] Internal Review for the Implicit Return Extension to the Enhanced Trace for RISC-V 2.0 (E-Trace) Specification Greetings! We are delighted to announce the commencement of the internal review period for the Implicit Return Extension to the Enhanced Trace for RISC-V 2.0 specification. This extension addresses a limitation with the Implicit Return capabilities defined in the E-Trace 2.0 specification. This 2-weeks review period begins today, 09-Jan-2026, and concludes on 23-Jan-2026. The specification document is available for download as a PDF at the following link: https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0%2BIRext/riscv-trace-spec-asciidoc.pdf The changes to the E-Trace spec can be seen here: https://github.com/riscv-non-isa/riscv-trace-spec/pull/264 The background to the issue being addressed can be found here: https://github.com/riscv-non-isa/riscv-trace-spec/issues/254 Important: please ensure you are subscribed to the respective Technical Committee mailing list at https://lists.riscv.org/g/soc-infra How to Provide Feedback: To participate in the review, you may either: Email your comments to https://lists.riscv.org/g/soc-infra, or Submit issues directly on the GitHub repository here: https://github.com/riscv-non-isa/riscv-trace-spec/issues If you encounter any issues accessing the document or GitHub links, please don't hesitate to contact [email protected]. Your Feedback Matters: During the review period, we will gather corrections, comments, and suggestions for review by the SoC Infra HC and DTPM SIG. We greatly appreciate your contributions and feedback in refining this specification. Warm regards, Iain Robertson (Fast-track author, DTPM SIG chair)
