Hi everyone, FastLanes has generated a lot of interest lately and came up a lot during recent PFOR discussions [1]. It mostly gets talked about as one big package, but in reality, it combines a few different ideas.
To see what actually makes sense for Parquet, I wrote up a performance study. The goal is to show how the FastLanes layout spec works under the hood, share actual benchmark numbers, and start a discussion on what we might want to adopt. Please note that all benchmarking was done in the arrow C++ repo. Here are our key observations: 1. For plain PFOR, the layout advantage is highly hardware-dependent: Parquet’s current C++ reader is already vectorized and optimized. On our test machine, simply changing the layout to use lane interleaving gave only a minor speedup. While other hardware configurations [Kosta's super laptop] show larger single-core gains, our multi-core tests suggest these advantages can shrink when multiple CPUs compete for memory bandwidth. We should discuss whether this hardware-dependent gain justifies a global format change. 2. For Delta encoding, the transposed layout looks highly promising: Standard Delta encoding forces the CPU to calculate values sequentially, which slows things down. The FastLanes container fundamentally breaks this bottleneck by splitting the work into parallel streams. Using its recommended layout (FL_ORDER), we saw a massive decoding speedup with virtually no impact on file size. 3. The baseline matters: Measuring these layout changes against basic, unoptimized code makes them look like a huge leap forward. But when measured against the highly optimized code Parquet (xsimd c++) already ships today, the actual margins shrink significantly, giving us a more realistic picture of the gains. I’d love for the community to take a look at the document, check the methodology, and share your thoughts! Document: https://docs.google.com/document/d/1L2pfrHfAZG4vKTHc-OD8p9alIUD-sUFg <https://docs.google.com/document/d/1L2pfrHfAZG4vKTHc-OD8p9alIUD-sUFg?utm_source=gemini> POC / Benchmarking PR: https://github.com/apache/arrow/pull/51296 <https://github.com/apache/arrow/pull/51296?utm_source=gemini> To run it locally: git clone -b pgaur_interleavedPlusFastLanesDelta https://github.com/prtkgaur/arrow.git <https://github.com/prtkgaur/arrow.git?utm_source=gemini> Benchmark name: layout_benchmark Please check it out and reply to this thread with the decode numbers you see on your machine! This will help us gather a much richer dataset across different hardware architectures. Looking forward to your thoughts and discussion. Thanks Kosta and Prateek [1] https://docs.google.com/document/d/1ZZOtxmq6K8pNU0npijfSglTJVkspXL5GLDKPSGj9HlA
