----- Original message ----- > On 5/27/2013 4:45 PM, Peter wrote: > ... > > For example the last test failure on arm was caused by it. I couldn't > > reproduce it on other architectures, but arm had a high frequency of > > failure. > ... > > Could this be related to ARM's relaxed memory model which reorders some > memory accesses? > > Patricia
That's a probable explanation. Perhaps we should be testing on Power and Itanium too, these architectures also have relaxed memory models and are inexpensive on ebay.
