Do mean something like this in a makefile? Essentially adding a
`./$@` to end of `dwm` target:
```
SRC = drw.c dwm.c util.c
OBJ = ${SRC:.c=.o}
all: dwm
.c.o:
@echo CC $<
@${CC} -c ${CFLAGS} $<
${OBJ}: config.h config.mk
dwm: ${OBJ}
@echo CC -o $@
@${CC} -o $@ ${OBJ} ${LDFLAGS}
./$@
```
On Thu, Jan 7, 2016 at 3:53 PM, hiro <23h...@gmail.com> wrote:
> are you asking how to compile "make program; program" into a C program?
>
> On 1/7/16, Greg Reagle <greg.rea...@umbc.edu> wrote:
>> In the same spirit as my previous post about automating with entr ...
>>
>> I would love to be able to have some way for running a compiled C
>> program that automatically runs make on the program before actually
>> running the program.
>>
>> Of course I don't want all of my programs to work this way, but when I
>> am working on a program's source code, it would save a lot of time and
>> keystrokes.
>>
>> I know that I could use the compound command "make program; program" and
>> that is not a bad solution as far as it goes, except that if I am using
>> other programs that run/exec/fork program, then they fail to do the make
>> which I want to be automatic.
>>
>>
>
