On Thu, Aug 15, 2019 at 04:54:12AM +0200, Marcin Wojtas wrote:
> This patch introduces all necessary components required
> for building EDK2 firmware for CN9131-DB setup A.
>
> In order to build this variant, '-D CN9131' flag should be added.
> Otherwise the default (CN9130) will be compiled.
Yeah, see comment on the CN9130 .dsc - if you change that as
requested, don't forget to update this commit message.
> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
> ---
> Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc |
> 72 ++++++++++++++
> Platform/Marvell/Cn913xDb/Cn913xDbA.dsc |
> 7 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf |
> 57 ++++++++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf |
> 22 +++++
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h |
> 2 +
> Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h |
> 2 +
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c |
> 29 ++++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl |
> 98 ++++++++++++++++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi |
> 26 +++---
> 9 files changed, 303 insertions(+), 12 deletions(-)
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
>
> diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> new file mode 100644
> index 0000000..7235b9f
> --- /dev/null
> +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> @@ -0,0 +1,72 @@
> +## @file
> +# Component description file for the CN9131 Development Board (variant A)
> +#
> +# Copyright (c) 2019 Marvell International Ltd.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsFixedAtBuild.common]
> + # CP115 count
> + gMarvellTokenSpaceGuid.PcdMaxCpCount|2
> +
> + # MPP
> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
> +
> + # CP115 #1 MPP
> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3,
> 0x3, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0, 0x0, 0x9, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7,
> 0x7, 0x2, 0x2, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0, 0x0, 0x0, 0x0 }
> +
> + # ComPhy
> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
> + # ComPhy1
> + # 0: PCIE0 5 Gbps
> + # 1: PCIE0 5 Gbps
> + # 2: UNCONNECTED
> + # 3: USB3_HOST1 5 Gbps
> + # 4: SFI 10.31 Gbps
> + # 5: SATA1 5 Gbps
> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0),
> $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)}
> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),
> $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
> +
> + # UtmiPhy
> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
> $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> +
> + # MDIO
> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
> +
> + # PHY
> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> +
> + # NET
> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
> $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) }
> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI),
> $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI) }
> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF }
> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
> +
> + # NonDiscoverableDevices
> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
> diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> index d77785d..5aca5a1 100644
> --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> @@ -13,7 +13,11 @@
> #
>
> ################################################################################
> [Defines]
> +!if $(CN9131)
> + PLATFORM_NAME = Cn9131DbA
> +!else
> PLATFORM_NAME = Cn9130DbA
> +!endif
> PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7
> PLATFORM_VERSION = 0.1
> DSC_SPECIFICATION = 0x0001000B
> @@ -34,6 +38,9 @@
>
> !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
> +!if $(CN9131)
> +!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> +!endif
>
> [Components.common]
> Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
> diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
> b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
> new file mode 100644
> index 0000000..bbf1b51
> --- /dev/null
> +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
> @@ -0,0 +1,57 @@
> +## @file
> +# Component description file for PlatformAcpiTables module.
> +#
> +# ACPI table data and ASL sources required to boot the platform.
> +#
> +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
> +# Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001B
> + BASE_NAME = PlatformAcpiTables
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Cn9131DbA/Ssdt.asl
> + Cn913xDbA/Dsdt.asl
> + Cn913xDbA/Mcfg.aslc
> + Fadt.aslc
> + Gtdt.aslc
> + Madt.aslc
> + Pptt.aslc
> + Spcr.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Marvell/Marvell.dec
> +
> +[FixedPcd]
> + gArmPlatformTokenSpaceGuid.PcdCoreCount
> +
> + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> +
> + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
> + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
> + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
> +
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> +
> +[BuildOptions]
> + *_*_*_ASLCC_FLAGS = -DCN9131
> diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
> b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
> new file mode 100644
> index 0000000..8108197
> --- /dev/null
> +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
> @@ -0,0 +1,22 @@
> +## @file
> +#
> +# Device tree description of the Marvell CN9130-DB-A platform
> +#
> +# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001B
> + BASE_NAME = Cn9131DbADeviceTree
> + FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 #
> gDtPlatformDefaultDtbFileGuid
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + cn9131-db-A.dts
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> diff --git
> a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> index 2533c35..6618737 100644
> ---
> a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> +++
> b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> @@ -15,5 +15,7 @@
> #define CN9130_DB_VBUS1_LIMIT_PIN 5
> #define CN9130_DB_SDMMC_VCC_PIN 14
> #define CN9130_DB_SDMMC_VCCQ_PIN 15
> +#define CN9131_DB_VBUS0_PIN 3
> +#define CN9131_DB_VBUS0_LIMIT_PIN 2
>
> #endif
> diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
> b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
> index b5fd397..2838676 100644
> --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
> +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
> @@ -18,6 +18,8 @@
>
> #if defined(CN9130)
> #define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ','
> ')
> +#elif defined (CN9131)
> +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','1',' ','
> ')
> #endif
>
> /**
> diff --git
> a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> index 598c649..dded150 100644
> ---
> a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> +++
> b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> @@ -91,6 +91,33 @@ Cp0XhciInit (
> MV_GPIO_DRIVER_TYPE_PCA95XX);
> }
>
> +STATIC CONST MV_GPIO_PIN mCp1XhciVbusPins[] = {
> + {
> + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
> + MV_GPIO_CP1_CONTROLLER0,
> + CN9131_DB_VBUS0_PIN,
> + TRUE,
> + },
> + {
> + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
> + MV_GPIO_CP1_CONTROLLER0,
> + CN9131_DB_VBUS0_LIMIT_PIN,
> + TRUE,
> + },
> +};
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +Cp1XhciInit (
> + IN NON_DISCOVERABLE_DEVICE *This
> + )
> +{
> + return ConfigurePins (mCp1XhciVbusPins,
> + ARRAY_SIZE (mCp1XhciVbusPins),
> + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
> +}
> +
> STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
> {
> MV_GPIO_DRIVER_TYPE_PCA95XX,
> @@ -130,6 +157,8 @@ NonDiscoverableDeviceInitializerGet (
> case 0:
> case 1:
> return Cp0XhciInit;
> + case 2:
> + return Cp1XhciInit;
> }
> }
>
> diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> new file mode 100644
> index 0000000..99bc751
> --- /dev/null
> +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> @@ -0,0 +1,98 @@
> +/** @file
> +
> + Secondary System Description Table Fields (SSDT)
> +
> + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "IcuInterrupts.h"
> +
> +DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
> +{
> + Scope (_SB)
> + {
> + Device (AHC1)
> + {
> + Name (_HID, "LNRO001E") // _HID: Hardware ID
> + Name (_UID, 0x00) // _UID: Unique ID
> + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
> + Name (_CLS, Package (0x03) // _CLS: Class Code
> + {
> + 0x01,
> + 0x06,
> + 0x01
> + })
> +
> + Name (_CRS, ResourceTemplate () // _CRS: Current Resource
> Settings
> + {
> + Memory32Fixed (ReadWrite,
> + 0xF4540000, // Address Base (MMIO)
> + 0x00030000, // Address Length
> + )
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,
> ,, )
> + {
> + CP_GIC_SPI_CP1_SATA_H0
> + }
> + })
> + }
> +
> + Device (XHC2)
> + {
> + Name (_HID, "PNP0D10") // _HID: Hardware ID
> + Name (_UID, 0x01) // _UID: Unique ID
> + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
> +
> + Name (_CRS, ResourceTemplate () // _CRS: Current Resource
> Settings
> + {
> + Memory32Fixed (ReadWrite,
> + 0xF4510000, // Address Base (MMIO)
> + 0x00004000, // Address Length
> + )
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,
> ,, )
> + {
> + CP_GIC_SPI_CP1_USB_H1
> + }
> + })
> + }
> + Device (PP21)
> + {
> + Name (_HID, "MRVL0110") // _HID:
> Hardware ID
> + Name (_CCA, 0x01) //
> Cache-coherent controller
> + Name (_UID, 0x00) // _UID:
> Unique ID
> + Name (_CRS, ResourceTemplate ()
> + {
> + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
> + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)
> + })
> + Name (_DSD, Package () {
> + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
> + Package () {
> + Package () { "clock-frequency", 333333333 },
> + }
> + })
> + Device (ETH0)
> + {
> + Name (_ADR, 0x0)
> + Name (_CRS, ResourceTemplate ()
> + {
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,
> ,, )
> + {
> + CP_GIC_SPI_PP2_CP1_PORT0
> + }
> + })
> + Name (_DSD, Package () {
> + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
> + Package () {
> + Package () { "port-id", 0 },
> + Package () { "gop-port-id", 0 },
> + Package () { "phy-mode", "10gbase-kr"},
> + }
> + })
> + }
> + }
> + }
> +}
> diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
> b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
> index c8e425a..9c9dfb6 100644
> --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
> +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
So, based on previous license comment, I think this needs to be broken
out as a separate patch (and go into edk2-non-osi).
/
Leif
> @@ -6,15 +6,23 @@
> */
>
> #undef CP110_NUM
> -#undef CP110_PCIE_MEM_SIZE
> +#undef CP110_NAME
> +#undef CP110_BASE
> +#undef CP110_PCIE0_BASE
> +#undef CP110_PCIE1_BASE
> +#undef CP110_PCIE2_BASE
> #undef CP110_PCIEx_CPU_MEM_BASE
> -#undef CP110_PCIEx_BUS_MEM_BASE
> +#undef CP110_PCIEx_MEM_BASE
>
> /* CP110-1 Settings */
> +#define CP110_NAME cp1
> #define CP110_NUM 1
> -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
> -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) *
> 0x1000000)
> -#define CP110_PCIEx_BUS_MEM_BASE(iface)
> (CP110_PCIEx_CPU_MEM_BASE(iface))
> +#define CP110_BASE f4000000
> +#define CP110_PCIE0_BASE f4600000
> +#define CP110_PCIE1_BASE f4620000
> +#define CP110_PCIE2_BASE f4640000
> +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
> +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
>
> #include "armada-cp110.dtsi"
>
> @@ -93,12 +101,6 @@
>
> &cp1_sata0 {
> status = "okay";
> - /* CON32 */
> - sata-port@1 {
> - status = "okay";
> - /* Generic PHY, providing serdes lanes */
> - phys = <&cp1_comphy5 1>;
> - };
> };
>
> /* U24 */
> @@ -138,7 +140,7 @@
>
> &cp1_syscon0 {
> cp1_pinctrl: pinctrl {
> - compatible = "marvell,cp115-standalone-pinctrl";
> + compatible = "marvell,armada-7k-pinctrl";
>
> cp1_i2c0_pins: cp1-i2c-pins-0 {
> marvell,pins = "mpp37", "mpp38";
> --
> 2.7.4
>
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