BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a RDTSC intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong <eric.d...@intel.com> Cc: Ray Ni <ray...@intel.com> Cc: Laszlo Ersek <ler...@redhat.com> Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com> --- .../X64/AMDSevVcCommon.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c index 697d50338da0..1b08a855cda0 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c @@ -895,6 +895,32 @@ CpuidExit ( return 0; } +STATIC +UINTN +RdtscExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINTN Status; + + Status = VmgExit (Ghcb, SvmExitRdtsc, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + VmgExit (Ghcb, SvmExitUnsupported, SvmExitRdtsc, 0); + ASSERT (0); + } + Regs->Rax = Ghcb->SaveArea.Rax; + Regs->Rdx = Ghcb->SaveArea.Rdx; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -911,6 +937,10 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitRdtsc: + NaeExit = RdtscExit; + break; + case SvmExitCpuid: NaeExit = CpuidExit; break; -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#50955): https://edk2.groups.io/g/devel/message/50955 Mute This Topic: https://groups.io/mt/60973111/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-